initial

chapter4/pcIMemTB.v

@@ -0,0 +1,29 @@
+module pcIMemTB();
+
+  reg rst;
+  reg clk;
+  wire [31:0] pc;
+  wire [31:0] next_pc;
+  wire [31:0] instr;
+
+pcIMem dut (
+  .clk(clk),
+  .rst(rst),
+  .pc(pc),
+  .instr(instr),
+  .next_pc(next_pc)
+);
+
+always begin 
+  clk = ~clk; #2;
+end
+
+initial begin
+  $dumpfile("pcIMem.vcd");
+  $dumpvars;
+  clk = 1'b0;
+  rst = 1'b1; #4;
+  rst = 1'b0; #38;
+  $finish;
+end
+endmodule