initial

chapter4/pcIMemDecTB.v

@@ -0,0 +1,56 @@
+`timescale 1ns/1ps
+
+module pcIMemDecTB();
+    // Inputs
+    reg clk;
+    reg rst;
+    
+    // Outputs
+    wire [31:0] pc;
+    wire [31:0] next_pc;
+    wire [31:0] instr;
+    
+    // Create test memory and program.hex FIRST
+    reg [31:0] test_mem [0:5];
+    initial begin
+        test_mem[0] = 32'h00001037;  // lui x0, 1
+        test_mem[1] = 32'h00100093;  // addi x1, x0, 1
+        test_mem[2] = 32'h001081b3;  // add x3, x1, x1
+        test_mem[3] = 32'h0010a023;  // sw x1, 0(x1)
+        test_mem[4] = 32'h00108663;  // beq x1, x1, 12
+        test_mem[5] = 32'h00c0006f;  // jal x0, 12
+        
+        $writememh("program.hex", test_mem);
+        #1; // Small delay to ensure file creation
+    end
+
+    // Instantiate DUT AFTER file creation
+    pcIMemDec dut (
+        .clk(clk),
+        .rst(rst),
+        .pc(pc),
+        .next_pc(next_pc),
+        .instr(instr)
+    );
+    
+    // Clock generation (100MHz)
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;
+    end
+    
+    // Test sequence
+    initial begin
+        $dumpfile("pcIMemDec.vcd");
+        $dumpvars(0, pcIMemDecTB);
+        
+        rst = 1;
+        #20 rst = 0;
+        
+        $monitor("Time=%0t PC=%h Instr=%h Types: U=%b I=%b R=%b S=%b B=%b J=%b",
+                 $time, pc, instr,
+                 dut.isUType, dut.isIType, dut.isRType, dut.isSType, dut.isBType, dut.isJType);
+        
+        #200 $finish;
+    end
+endmodule