initial

chapter2/fullAdder.v

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+module fulladder (
+  input in1,
+  input in2,
+  input carryIn,
+  output sum,
+  output carryO
+);
+
+wire xor1, and1, and2;
+
+xor x1 (xor1, in1, in2);
+xor x2 (sum, xor1, carryIn);
+
+and a1 (and1, xor1, carryIn);
+and a2 (and2, in1, in2);
+
+or o1 (carryO, and1, and2);
+
+endmodule