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kaltinsoy
2025-08-18 07:18:32 +03:00
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99
chapter2/a.out Executable file
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib64/ivl/system.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib64/ivl/v2005_math.vpi";
:vpi_module "/usr/lib64/ivl/va_math.vpi";
S_0x56542d3760c0 .scope module, "fibonacciTB" "fibonacciTB" 2 1;
.timescale 0 0;
v0x56542d388680_0 .var "clk", 0 0;
v0x56542d388750_0 .net "num", 31 0, v0x56542d388390_0; 1 drivers
v0x56542d388820_0 .var "rst", 0 0;
S_0x56542d376250 .scope module, "uut" "fibonacci" 2 6, 3 1 0, S_0x56542d3760c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /OUTPUT 32 "num";
v0x56542d3764a0_0 .net "clk", 0 0, v0x56542d388680_0; 1 drivers
v0x56542d388390_0 .var "num", 31 0;
v0x56542d388470 .array "nums", 0 1, 31 0;
v0x56542d388540_0 .net "rst", 0 0, v0x56542d388820_0; 1 drivers
E_0x56542d373800 .event posedge, v0x56542d3764a0_0;
.scope S_0x56542d376250;
T_0 ;
%wait E_0x56542d373800;
%load/vec4 v0x56542d388540_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 1, 0, 32;
%assign/vec4 v0x56542d388390_0, 0;
%pushi/vec4 0, 0, 32;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x56542d388470, 0, 4;
%pushi/vec4 0, 0, 32;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x56542d388470, 0, 4;
%jmp T_0.1;
T_0.0 ;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x56542d388470, 4;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x56542d388470, 4;
%add;
%assign/vec4 v0x56542d388390_0, 0;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x56542d388470, 4;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x56542d388470, 0, 4;
%load/vec4 v0x56542d388390_0;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x56542d388470, 0, 4;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_0x56542d3760c0;
T_1 ;
%load/vec4 v0x56542d388680_0;
%inv;
%store/vec4 v0x56542d388680_0, 0, 1;
%delay 1, 0;
%jmp T_1;
.thread T_1;
.scope S_0x56542d3760c0;
T_2 ;
%vpi_call 2 17 "$dumpfile", "fibonacci.vcd" {0 0 0};
%vpi_call 2 18 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56542d388680_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56542d388820_0, 0, 1;
%delay 1, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56542d388820_0, 0, 1;
%delay 1, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56542d388820_0, 0, 1;
%delay 10, 0;
%vpi_call 2 23 "$finish" {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"fibonacciTB.v";
"fibonacci.v";

83
chapter2/calculator Executable file
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib64/ivl/system.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib64/ivl/v2005_math.vpi";
:vpi_module "/usr/lib64/ivl/va_math.vpi";
S_0x55fa39636f10 .scope module, "calculator" "calculator" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 32 "A";
.port_info 1 /INPUT 32 "B";
.port_info 2 /INPUT 2 "op";
.port_info 3 /OUTPUT 32 "Y";
L_0x7feabdea7018 .functor BUFT 1, C4<0000000000000000000000000000zzzz>, C4<0>, C4<0>, C4<0>;
v0x55fa39635140_0 .net "A", 31 0, L_0x7feabdea7018; 1 drivers
o0x7feabdef0048 .functor BUFZ 4, C4<zzzz>; HiZ drive
v0x55fa39610eb0_0 .net "A_rand", 3 0, o0x7feabdef0048; 0 drivers
L_0x7feabdea7060 .functor BUFT 1, C4<00000000000000000000000000zzzzzz>, C4<0>, C4<0>, C4<0>;
v0x55fa3965a2a0_0 .net "B", 31 0, L_0x7feabdea7060; 1 drivers
o0x7feabdef00a8 .functor BUFZ 6, C4<zzzzzz>; HiZ drive
v0x55fa3965a360_0 .net "B_rand", 5 0, o0x7feabdef00a8; 0 drivers
v0x55fa3965a440_0 .var "Y", 31 0;
o0x7feabdef0108 .functor BUFZ 2, C4<zz>; HiZ drive
v0x55fa3965a570_0 .net "op", 1 0, o0x7feabdef0108; 0 drivers
E_0x55fa39647e70 .event anyedge, v0x55fa3965a570_0, v0x55fa39635140_0, v0x55fa3965a2a0_0;
.scope S_0x55fa39636f10;
T_0 ;
%wait E_0x55fa39647e70;
%load/vec4 v0x55fa3965a570_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_0.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_0.3, 6;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55fa3965a440_0, 0, 32;
%jmp T_0.5;
T_0.0 ;
%load/vec4 v0x55fa39635140_0;
%load/vec4 v0x55fa3965a2a0_0;
%add;
%store/vec4 v0x55fa3965a440_0, 0, 32;
%jmp T_0.5;
T_0.1 ;
%load/vec4 v0x55fa39635140_0;
%load/vec4 v0x55fa3965a2a0_0;
%sub;
%store/vec4 v0x55fa3965a440_0, 0, 32;
%jmp T_0.5;
T_0.2 ;
%load/vec4 v0x55fa39635140_0;
%load/vec4 v0x55fa3965a2a0_0;
%mul;
%store/vec4 v0x55fa3965a440_0, 0, 32;
%jmp T_0.5;
T_0.3 ;
%load/vec4 v0x55fa39635140_0;
%load/vec4 v0x55fa3965a2a0_0;
%div;
%store/vec4 v0x55fa3965a440_0, 0, 32;
%jmp T_0.5;
T_0.5 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"calculator.v";

45
chapter2/calculator.v Normal file
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module calculator (
input [1:0] op,
input clk,
input rst,
output reg [31:0] Y
);
reg [31:0] A;
reg [31:0] B;
wire [5:0] B_rand;
wire [3:0] A_rand;
reg [31:0] Y_prev;
assign A = {{28{1'b0}}, A_rand[5:0]};
assign B = {{26{1'b0}}, B_rand[3:0]};
always @(*) begin
if(!rst) begin
case(op)
2'b00 :Y = A + B;
2'b01 :Y = A - B;
2'b10 :Y = A * B;
2'b11 :Y = A / B;
default: Y = 0;
endcase
end
else begin
Y = 0;
end
end
always @(posedge clk) begin
if (rst) begin
Y_prev <= 32'd0;
A <= 32'd0;
B <= 32'd0;
end
else begin
Y_prev <= Y;
A <= Y_prev;
end
end
endmodule

96
chapter2/fibonacci Executable file
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib64/ivl/system.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib64/ivl/v2005_math.vpi";
:vpi_module "/usr/lib64/ivl/va_math.vpi";
S_0x562127b680c0 .scope module, "fibonacciTB" "fibonacciTB" 2 1;
.timescale 0 0;
v0x562127b7a290_0 .var "clk", 0 0;
v0x562127b7a360_0 .net "num", 31 0, v0x562127b79fa0_0; 1 drivers
v0x562127b7a430_0 .var "rst", 0 0;
S_0x562127b68250 .scope module, "uut" "fibonacci" 2 6, 3 1 0, S_0x562127b680c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /OUTPUT 32 "num";
v0x562127b68480_0 .net "clk", 0 0, v0x562127b7a290_0; 1 drivers
v0x562127b79fa0_0 .var "num", 31 0;
v0x562127b7a080 .array "nums", 0 1, 31 0;
v0x562127b7a150_0 .net "rst", 0 0, v0x562127b7a430_0; 1 drivers
E_0x562127b65800 .event posedge, v0x562127b68480_0;
.scope S_0x562127b68250;
T_0 ;
%wait E_0x562127b65800;
%load/vec4 v0x562127b7a150_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 1, 0, 32;
%assign/vec4 v0x562127b79fa0_0, 0;
%pushi/vec4 0, 0, 32;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x562127b7a080, 0, 4;
%pushi/vec4 0, 0, 32;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x562127b7a080, 0, 4;
%jmp T_0.1;
T_0.0 ;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x562127b7a080, 4;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x562127b7a080, 0, 4;
%load/vec4 v0x562127b79fa0_0;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x562127b7a080, 0, 4;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x562127b7a080, 4;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x562127b7a080, 4;
%add;
%assign/vec4 v0x562127b79fa0_0, 0;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_0x562127b680c0;
T_1 ;
%load/vec4 v0x562127b7a290_0;
%inv;
%store/vec4 v0x562127b7a290_0, 0, 1;
%delay 1, 0;
%jmp T_1;
.thread T_1;
.scope S_0x562127b680c0;
T_2 ;
%vpi_call 2 17 "$dumpfile", "fibonacci.vcd" {0 0 0};
%vpi_call 2 18 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x562127b7a290_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x562127b7a430_0, 0, 1;
%delay 4, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x562127b7a430_0, 0, 1;
%delay 40, 0;
%vpi_call 2 21 "$finish" {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"fibonacciTB.v";
"fibonacci.v";

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chapter2/fibonacci.v Normal file
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module fibonacci (
input clk,
input rst,
output reg [31:0] num
);
reg [31:0] nums [1:0];
always @(posedge clk) begin
if (rst) begin
num <= 32'd1;
nums[0] <= 32'd0;
nums[1] <= 32'd0;
end
else begin
nums[1] <= nums[0];
nums[0] <= num;
num <= nums[0] + nums[1];
end
end
endmodule

155
chapter2/fibonacci.vcd Normal file
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$date
Sun Aug 17 18:49:30 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module fibonacciTB $end
$var wire 32 ! num [31:0] $end
$var reg 1 " clk $end
$var reg 1 # rst $end
$scope module uut $end
$var wire 1 " clk $end
$var wire 1 # rst $end
$var reg 32 $ num [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
bx $
1#
0"
bx !
$end
#1
b1 !
b1 $
1"
#2
0"
#3
1"
#4
0"
0#
#5
b0 !
b0 $
1"
#6
0"
#7
b1 !
b1 $
1"
#8
0"
#9
1"
#10
0"
#11
1"
#12
0"
#13
b10 !
b10 $
1"
#14
0"
#15
1"
#16
0"
#17
b11 !
b11 $
1"
#18
0"
#19
b100 !
b100 $
1"
#20
0"
#21
b101 !
b101 $
1"
#22
0"
#23
b111 !
b111 $
1"
#24
0"
#25
b1001 !
b1001 $
1"
#26
0"
#27
b1100 !
b1100 $
1"
#28
0"
#29
b10000 !
b10000 $
1"
#30
0"
#31
b10101 !
b10101 $
1"
#32
0"
#33
b11100 !
b11100 $
1"
#34
0"
#35
b100101 !
b100101 $
1"
#36
0"
#37
b110001 !
b110001 $
1"
#38
0"
#39
b1000001 !
b1000001 $
1"
#40
0"
#41
b1010110 !
b1010110 $
1"
#42
0"
#43
b1110010 !
b1110010 $
1"
#44
0"

23
chapter2/fibonacciTB.v Normal file
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module fibonacciTB();
reg clk, rst;
wire [31:0] num;
fibonacci uut (
.clk(clk),
.rst(rst),
.num(num)
);
always begin
clk = ~clk; #1;
end
initial begin
$dumpfile("fibonacci.vcd");
$dumpvars;
clk = 1'b0; rst = 1'b1; #4;
rst = 1'b0; #40;
$finish;
end
endmodule

19
chapter2/fullAdder.v Normal file
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module fulladder (
input in1,
input in2,
input carryIn,
output sum,
output carryO
);
wire xor1, and1, and2;
xor x1 (xor1, in1, in2);
xor x2 (sum, xor1, carryIn);
and a1 (and1, xor1, carryIn);
and a2 (and2, in1, in2);
or o1 (carryO, and1, and2);
endmodule

39
chapter2/invGate Executable file
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib64/ivl/system.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib64/ivl/v2005_math.vpi";
:vpi_module "/usr/lib64/ivl/va_math.vpi";
S_0x56122ac89ed0 .scope module, "invGateTB" "invGateTB" 2 1;
.timescale 0 0;
v0x56122ac99480_0 .var "A", 0 0;
v0x56122ac99520_0 .net "B", 0 0, L_0x56122ac995f0; 1 drivers
S_0x56122ac8a060 .scope module, "uut" "invGate" 2 6, 3 1 0, S_0x56122ac89ed0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /OUTPUT 1 "B";
L_0x56122ac995f0 .functor NOT 1, v0x56122ac99480_0, C4<0>, C4<0>, C4<0>;
v0x56122ac77570_0 .net "A", 0 0, v0x56122ac99480_0; 1 drivers
v0x56122ac99360_0 .net "B", 0 0, L_0x56122ac995f0; alias, 1 drivers
.scope S_0x56122ac89ed0;
T_0 ;
%vpi_call 2 12 "$dumpfile", "invGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122ac99480_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122ac99480_0, 0, 1;
%delay 10, 0;
%vpi_call 2 16 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"invGateTB.v";
"invGate.v";

8
chapter2/invGate.v Normal file
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module invGate (
input A,
output B
);
not a1 (B, A);
endmodule

30
chapter2/invGate.vcd Normal file
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$date
Sun Aug 17 06:21:41 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module invGateTB $end
$var wire 1 ! B $end
$var reg 1 " A $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 ! B $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
1"
0!
$end
#10
1!
0"
#20

19
chapter2/invGateTB.v Normal file
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module invGateTB();
reg A;
wire B;
invGate uut (
.A(A),
.B(B)
);
initial begin
$dumpfile("invGate.vcd");
$dumpvars;
A = 1'b1; #10;
A = 1'b0; #10;
$finish;
end
endmodule

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chapter2/mux.v Normal file
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module mux (
input [1:0] A,
input S,
output Y
);
wire and1, and2;
and a1 (and1, A[0], S);
and a2 (and2, A[1], ~S);
or o1 (Y, and1, and2);
endmodule