26 lines
1.3 KiB
XML
26 lines
1.3 KiB
XML
<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW2A-18" pn="GW2A-LV18PG256C8/I7">gw2a18-002</Device>
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<FileList>
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<File path="src/ALU.v" type="file.verilog" enable="1"/>
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<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
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<File path="src/addition.v" type="file.verilog" enable="1"/>
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<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
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<File path="src/dabble.v" type="file.verilog" enable="1"/>
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<File path="src/fulladder.v" type="file.verilog" enable="1"/>
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<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
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<File path="src/halfadder.v" type="file.verilog" enable="1"/>
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<File path="src/halfsubtraction.v" type="file.verilog" enable="1"/>
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<File path="src/logicUnit.v" type="file.verilog" enable="1"/>
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<File path="src/multiplier.v" type="file.verilog" enable="1"/>
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<File path="src/opCode.v" type="file.verilog" enable="1"/>
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<File path="src/selector.v" type="file.verilog" enable="1"/>
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<File path="src/subtraction.v" type="file.verilog" enable="1"/>
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<File path="src/top.v" type="file.verilog" enable="1"/>
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<File path="src/top.cst" type="file.cst" enable="1"/>
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</FileList>
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</Project>
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