Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\koray\Documents\gowin\ALU\src\addition.v C:\Users\koray\Documents\gowin\ALU\src\ALU.v C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v C:\Users\koray\Documents\gowin\ALU\src\dabble.v C:\Users\koray\Documents\gowin\ALU\src\fulladder.v C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v C:\Users\koray\Documents\gowin\ALU\src\halfadder.v C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v C:\Users\koray\Documents\gowin\ALU\src\multiplier.v C:\Users\koray\Documents\gowin\ALU\src\opCode.v C:\Users\koray\Documents\gowin\ALU\src\selector.v C:\Users\koray\Documents\gowin\ALU\src\subtraction.v C:\Users\koray\Documents\gowin\ALU\src\top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Thu Jan 23 05:43:09 2025 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 402.914MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 402.914MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 402.914MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 402.914MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 402.914MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 28 |
| I/O Buf | 28 |
|     IBUF | 14 |
|     OBUF | 14 |
| LUT | 141 |
|     LUT2 | 16 |
|     LUT3 | 36 |
|     LUT4 | 89 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 141(141 LUT, 0 ALU) / 20736 | <1% |
| Register | 0 / 16173 | 0% |
|   --Register as Latch | 0 / 16173 | 0% |
|   --Register as FF | 0 / 16173 | 0% |
| BSRAM | 0 / 46 | 0% |