initial commit

2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
--- a/verilog/ALUTangTest/halfsubtraction.v
+++ b/verilog/ALUTangTest/halfsubtraction.v
@ -0,0 +1,12 @@
+module halfsubtraction (
+    input A, B,
+    output Difference, Borrow
+);
+
+wire notA;
+
+xor xo1 (Difference, A, B);
+not a1 (notA, A);
+and an1 (Borrow, notA, B);
+
+endmodule