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verilog/ALUTangTest/fullsubtraction.v

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+module fullsubtraction (
+    input A, B, BorrowIN,
+    output Difference, BorrowOut
+);
+
+wire tempD, tempB1, tempB2;
+
+halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
+halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
+or o1 (BorrowOut, tempB1, tempB2);
+
+endmodule