initial commit

2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
--- a/verilog/ALUTangTest/ALU
+++ b/verilog/ALUTangTest/ALU
--- a/verilog/ALUTangTest/ALU.v
+++ b/verilog/ALUTangTest/ALU.v
@ -0,0 +1,79 @@
+module ALU (
+    input [3:0] A, B,
+    input CarryIN,
+    input [2:0] opCodeA,
+    output [11:0] bcd,
+    output CarryOUT, overflow
+);
+
+// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
+
+wire [7:0] opCode8;
+wire [3:0] add_Y, sub_Y;
+wire [3:0] resultA, resultO, resultX, lUOutput1;
+wire [3:0] aUtemp1, aUtemp2, lUOutput2;
+wire [3:0] wireY, wireLA;
+wire [7:0] opwireM, wireM, Y;
+
+opCode opCd (.A(opCodeA), .opCode(opCode8));
+
+arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
+logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
+multiplier mU (.A(A), .B(B), .Y(opwireM));
+
+or o01 (lUOutput1[0], resultA[0], resultO[0]);
+or o02 (lUOutput1[1], resultA[1], resultO[1]);
+or o03 (lUOutput1[2], resultA[2], resultO[2]);
+or o04 (lUOutput1[3], resultA[3], resultO[3]);
+
+or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
+or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
+or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
+or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
+
+
+and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
+and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
+and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
+and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
+
+
+and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
+and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
+and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
+and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
+
+and a21 (wireM[0], opCode8[2], opwireM[0]);
+and a22 (wireM[1], opCode8[2], opwireM[1]);
+and a23 (wireM[2], opCode8[2], opwireM[2]);
+and a24 (wireM[3], opCode8[2], opwireM[3]);
+and a25 (wireM[4], opCode8[2], opwireM[4]);
+and a26 (wireM[5], opCode8[2], opwireM[5]);
+and a27 (wireM[6], opCode8[2], opwireM[6]);
+and a28 (wireM[7], opCode8[2], opwireM[7]);
+
+
+or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
+or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
+or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
+or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
+
+
+or o1 (wireLA[0], lUOutput2[0], wireY[0]);
+or o2 (wireLA[1], lUOutput2[1], wireY[1]);
+or o3 (wireLA[2], lUOutput2[2], wireY[2]);
+or o4 (wireLA[3], lUOutput2[3], wireY[3]);
+
+or o31 (Y[0], wireLA[0], wireM[0]);
+or o32 (Y[1], wireLA[1], wireM[1]);
+or o33 (Y[2], wireLA[2], wireM[2]);
+or o34 (Y[3], wireLA[3], wireM[3]);
+or o35 (Y[4], 1'b0, wireM[4]);
+or o36 (Y[5], 1'b0, wireM[5]);
+or o37 (Y[6], 1'b0, wireM[6]);
+or o38 (Y[7], 1'b0, wireM[7]);
+
+BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
+
+
+endmodule
--- a/verilog/ALUTangTest/ALU.vcd
+++ b/verilog/ALUTangTest/ALU.vcd
--- a/verilog/ALUTangTest/ALU.vcdZone.Identifier
+++ b/verilog/ALUTangTest/ALU.vcdZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/ALU.vZone.Identifier
+++ b/verilog/ALUTangTest/ALU.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/ALUtb.v
+++ b/verilog/ALUTangTest/ALUtb.v
@ -0,0 +1,26 @@
+module ALUtb();
+
+reg [3:0] A,B;
+reg CarryIN;
+reg [2:0] opCodeA;
+wire CarryOUT, overflow;
+wire [7:0] Y;
+
+ALU uut (
+    .A(A),
+    .B(B),
+    .CarryIN(CarryIN),
+    .opCodeA(opCodeA),
+    .CarryOUT(CarryOUT),
+    .overflow(overflow),
+    .Y(Y)
+);
+
+initial begin
+    $dumpfile("ALU.vcd");
+    $dumpvars;
+    A = 4'b1111; B = 4'b0001; CarryIN = 1'b0; opCodeA = 3'b001; #5;
+    $finish;
+end
+
+endmodule
--- a/verilog/ALUTangTest/ALUtb.vZone.Identifier
+++ b/verilog/ALUTangTest/ALUtb.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/ALUZone.Identifier
+++ b/verilog/ALUTangTest/ALUZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/BinaryToBCD.v
+++ b/verilog/ALUTangTest/BinaryToBCD.v
@ -0,0 +1,79 @@
+module BinaryToBCD (
+    input [7:0] binary,
+    output [11:0] bcd
+);
+
+wire empty1, empty2;
+wire [3:0] dab1, dab2, dab3, dab4, dab5;
+
+and a111 (empty1, 1'b0, 1'b0);
+and a000 (empty2, 1'b0, 1'b0);
+and a222 (bcd[11], 1'b0, 1'b0);
+and a223 (bcd[10], 1'b0, 1'b0);
+
+dabble d1t (.A((empty1)),
+.B(binary[7]),
+.C(binary[6]),
+.D(binary[5]),
+.X(dab1[0]),
+.Y(dab1[1]),
+.Z(dab1[2]),
+.E(dab1[3]));
+
+dabble d2u (.A((dab1[1])),
+.B(dab1[2]),
+.C(dab1[3]),
+.D(binary[4]),
+.X(dab2[0]),
+.Y(dab2[1]),
+.Z(dab2[2]),
+.E(dab2[3]));
+
+dabble d3v (.A((dab2[1])),
+.B(dab2[2]),
+.C(dab2[3]),
+.D(binary[3]),
+.X(dab3[0]),
+.Y(dab3[1]),
+.Z(dab3[2]),
+.E(dab3[3]));
+
+dabble d4w (.A((empty2)),
+.B(dab1[0]),
+.C(dab2[0]),
+.D(dab3[0]),
+.X(bcd[9]),
+.Y(dab4[1]),
+.Z(dab4[2]),
+.E(dab4[3]));
+
+dabble d5x (.A((dab3[1])),
+.B(dab3[2]),
+.C(dab3[3]),
+.D(binary[2]),
+.X(dab5[0]),
+.Y(dab5[1]),
+.Z(dab5[2]),
+.E(dab5[3]));
+
+dabble d6y (.A((dab4[1])),
+.B(dab4[2]),
+.C(dab4[3]),
+.D(dab5[0]),
+.X(bcd[8]),
+.Y(bcd[7]),
+.Z(bcd[6]),
+.E(bcd[5]));
+
+dabble d7z (.A((dab5[1])),
+.B(dab5[2]),
+.C(dab5[3]),
+.D(binary[1]),
+.X(bcd[4]),
+.Y(bcd[3]),
+.Z(bcd[2]),
+.E(bcd[1]));
+
+or o1 (bcd[0], binary[0], 1'b0);
+
+endmodule
--- a/verilog/ALUTangTest/BinaryToBCD.vZone.Identifier
+++ b/verilog/ALUTangTest/BinaryToBCD.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/addition.v
+++ b/verilog/ALUTangTest/addition.v
@ -0,0 +1,20 @@
+module addition (
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [2:0] Carry4;
+
+fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
+fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
+fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
+fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
+
+
+//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
+xor ov1 (overflow, Carry4[2], CarryOUT);
+
+endmodule
--- a/verilog/ALUTangTest/addition.vZone.Identifier
+++ b/verilog/ALUTangTest/addition.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/arithmeticUnit.v
+++ b/verilog/ALUTangTest/arithmeticUnit.v
@ -0,0 +1,33 @@
+module arithmeticUnit (
+    input [1:0] opCode,
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] add_Y, sub_Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [3:0] addY, subY;
+wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
+
+addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
+subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
+
+and add1 (add_Y[0], opCode[0], addY[0]);
+and add2 (add_Y[1], opCode[0], addY[1]);
+and add3 (add_Y[2], opCode[0], addY[2]);
+and add4 (add_Y[3], opCode[0], addY[3]);
+
+and sub1 (sub_Y[0], opCode[1], subY[0]);
+and sub2 (sub_Y[1], opCode[1], subY[1]);
+and sub3 (sub_Y[2], opCode[1], subY[2]);
+and sub4 (sub_Y[3], opCode[1], subY[3]);
+
+// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
+and and10 (tempCSub, CarryOUTSUB, opCode[1]);
+and and11 (tempCAdd, CarryOUTADD, opCode[0]);
+or or4 (CarryOUT, tempCAdd, tempCSub);
+
+and add12 (overflow, opCode[0], tempoverflow);
+
+endmodule
--- a/verilog/ALUTangTest/arithmeticUnit.vZone.Identifier
+++ b/verilog/ALUTangTest/arithmeticUnit.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/compile.sh
+++ b/verilog/ALUTangTest/compile.sh
@ -0,0 +1,10 @@
+#!/bin/bash
+
+# Granting execute permissions to this script (one-time setup)
+# chmod +x script_name.sh
+
+# Using Icarus Verilog to compile Verilog files for simulation
+iverilog -o top top.v topTB.v ALU.v selector.v BinaryToBCD.v arithmeticUnit.v logicUnit.v multiplier.v opCode.v addition.v dabble.v subtraction.v fulladder.v fullsubtraction.v halfadder.v halfsubtraction.v
+
+# Running the simulation
+vvp top
--- a/verilog/ALUTangTest/compile.shZone.Identifier
+++ b/verilog/ALUTangTest/compile.shZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/dabble.v
+++ b/verilog/ALUTangTest/dabble.v
@ -0,0 +1,22 @@
+module dabble (
+    input A, B, C, D,
+    output X, Y, Z, E
+);
+
+wire xor1, nor1, xor2, nor2, nor3, or1;
+
+xor xo1 (xor1, A, D);
+nor no1 (nor1, A, B);
+xor xo2 (xor2, A, C);
+
+nor no2 (nor2, xor1, xor2);
+
+nor no3 (nor3, nor2, nor1);
+buf bu1 (X, nor3);
+or o1 (or1, xor1, nor1);
+
+nor no4 (Y, or1, C);
+and an1 (Z, or1, xor2);
+xor xo3 (E, nor3, D);
+
+endmodule
--- a/verilog/ALUTangTest/dabble.vZone.Identifier
+++ b/verilog/ALUTangTest/dabble.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/fulladder.v
+++ b/verilog/ALUTangTest/fulladder.v
@ -0,0 +1,12 @@
+module fulladder (
+    input A, B, Carry,
+    output Sum, CarryO
+);
+
+wire xor1, and1, and2;
+
+halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
+halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
+or o1 (CarryO, and1, and2);
+
+endmodule
--- a/verilog/ALUTangTest/fulladder.vZone.Identifier
+++ b/verilog/ALUTangTest/fulladder.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/fullsubtraction.v
+++ b/verilog/ALUTangTest/fullsubtraction.v
@ -0,0 +1,12 @@
+module fullsubtraction (
+    input A, B, BorrowIN,
+    output Difference, BorrowOut
+);
+
+wire tempD, tempB1, tempB2;
+
+halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
+halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
+or o1 (BorrowOut, tempB1, tempB2);
+
+endmodule
--- a/verilog/ALUTangTest/fullsubtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/fullsubtraction.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/halfadder.v
+++ b/verilog/ALUTangTest/halfadder.v
@ -0,0 +1,9 @@
+module halfadder (
+    input A, B,
+    output Sum, Carry
+);
+
+and a1 (Carry, A, B);
+xor xo1 (Sum, A, B);
+
+endmodule
--- a/verilog/ALUTangTest/halfadder.vZone.Identifier
+++ b/verilog/ALUTangTest/halfadder.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/halfsubtraction.v
+++ b/verilog/ALUTangTest/halfsubtraction.v
@ -0,0 +1,12 @@
+module halfsubtraction (
+    input A, B,
+    output Difference, Borrow
+);
+
+wire notA;
+
+xor xo1 (Difference, A, B);
+not a1 (notA, A);
+and an1 (Borrow, notA, B);
+
+endmodule
--- a/verilog/ALUTangTest/halfsubtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/halfsubtraction.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/logicUnit.v
+++ b/verilog/ALUTangTest/logicUnit.v
@ -0,0 +1,39 @@
+module logicUnit (
+    input [2:0] opCode,
+    input [3:0] A, B,
+    output [3:0] resultA, resultO, resultX
+);
+
+wire [3:0] and1, or1, xor1;
+
+and a01 (and1[0], A[0], B[0]);
+and a02 (and1[1], A[1], B[1]);
+and a03 (and1[2], A[2], B[2]);
+and a04 (and1[3], A[3], B[3]);
+
+or o01 (or1[0], A[0], B[0]);
+or o02 (or1[1], A[1], B[1]);
+or o03 (or1[2], A[2], B[2]);
+or o04 (or1[3], A[3], B[3]);
+
+xor xor01 (xor1[0], A[0], B[0]);
+xor xor02 (xor1[1], A[1], B[1]);
+xor xor03 (xor1[2], A[2], B[2]);
+xor xor04 (xor1[3], A[3], B[3]);
+
+and a_o1 (resultA[0], opCode[0], and1[0]);
+and a_o2 (resultA[1], opCode[0], and1[1]);
+and a_o3 (resultA[2], opCode[0], and1[2]);
+and a_o4 (resultA[3], opCode[0], and1[3]);
+
+and o_o1 (resultO[0], opCode[1], or1[0]);
+and o_o2 (resultO[1], opCode[1], or1[1]);
+and o_o3 (resultO[2], opCode[1], or1[2]);
+and o_o4 (resultO[3], opCode[1], or1[3]);
+
+and x_o1 (resultX[0], opCode[2], xor1[0]);
+and x_o2 (resultX[1], opCode[2], xor1[1]);
+and x_o3 (resultX[2], opCode[2], xor1[2]);
+and x_o4 (resultX[3], opCode[2], xor1[3]);
+
+endmodule
--- a/verilog/ALUTangTest/logicUnit.vZone.Identifier
+++ b/verilog/ALUTangTest/logicUnit.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/mult
+++ b/verilog/ALUTangTest/mult
@ -0,0 +1,782 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x560808805dd0 .scope module, "multTB" "multTB" 2 1;
+ .timescale 0 0;
+v0x56080883b1b0_0 .var "A", 3 0;
+v0x56080883b2a0_0 .var "B", 3 0;
+v0x56080883b370_0 .net "Y", 7 0, L_0x560808846dd0;  1 drivers
+S_0x560808804330 .scope module, "uut" "multiplier" 2 6, 3 1 0, S_0x560808805dd0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /OUTPUT 8 "Y";
+L_0x56080883b470 .functor AND 1, L_0x56080883b570, L_0x56080883b660, C4<1>, C4<1>;
+L_0x56080883b7a0 .functor AND 1, L_0x56080883b810, L_0x56080883b900, C4<1>, C4<1>;
+L_0x56080883ba20 .functor AND 1, L_0x56080883ba90, L_0x56080883bb80, C4<1>, C4<1>;
+L_0x56080883bc60 .functor AND 1, L_0x56080883bd00, L_0x56080883bda0, C4<1>, C4<1>;
+L_0x7f3ea6b4d018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+L_0x56080883c0c0 .functor NOT 1, L_0x7f3ea6b4d018, C4<0>, C4<0>, C4<0>;
+L_0x56080883c1d0 .functor AND 1, L_0x56080883c280, L_0x56080883c3d0, C4<1>, C4<1>;
+L_0x56080883c470 .functor AND 1, L_0x56080883c4e0, L_0x56080883c640, C4<1>, C4<1>;
+L_0x56080883c730 .functor AND 1, L_0x56080883c7f0, L_0x56080883c960, C4<1>, C4<1>;
+L_0x56080883c5d0 .functor AND 1, L_0x56080883cd10, L_0x56080883ce00, C4<1>, C4<1>;
+L_0x56080883ef10 .functor AND 1, L_0x56080883f360, L_0x56080883cef0, C4<1>, C4<1>;
+L_0x56080883f4b0 .functor AND 1, L_0x56080883f520, L_0x56080883f680, C4<1>, C4<1>;
+L_0x56080883f720 .functor AND 1, L_0x56080883f800, L_0x56080883f9c0, C4<1>, C4<1>;
+L_0x56080883fd70 .functor AND 1, L_0x56080883fe30, L_0x56080883ff20, C4<1>, C4<1>;
+L_0x5608088423d0 .functor AND 1, L_0x5608088429c0, L_0x560808842a60, C4<1>, C4<1>;
+L_0x56080883f790 .functor AND 1, L_0x560808842c10, L_0x560808842cb0, C4<1>, C4<1>;
+L_0x560808842ec0 .functor AND 1, L_0x560808842fc0, L_0x5608088430b0, C4<1>, C4<1>;
+L_0x5608088435d0 .functor AND 1, L_0x560808843690, L_0x5608088438c0, C4<1>, C4<1>;
+L_0x7f3ea6b4d138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x560808845900 .functor OR 1, L_0x560808845f60, L_0x7f3ea6b4d138, C4<0>, C4<0>;
+L_0x7f3ea6b4d180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x560808846160 .functor OR 1, L_0x5608088461d0, L_0x7f3ea6b4d180, C4<0>, C4<0>;
+L_0x7f3ea6b4d1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x560808846310 .functor OR 1, L_0x560808845ec0, L_0x7f3ea6b4d1c8, C4<0>, C4<0>;
+L_0x7f3ea6b4d210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x560808846690 .functor OR 1, L_0x560808846700, L_0x7f3ea6b4d210, C4<0>, C4<0>;
+L_0x7f3ea6b4d258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x560808846840 .functor OR 1, L_0x560808846970, L_0x7f3ea6b4d258, C4<0>, C4<0>;
+L_0x7f3ea6b4d2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x560808846c70 .functor OR 1, L_0x560808846ce0, L_0x7f3ea6b4d2a0, C4<0>, C4<0>;
+L_0x7f3ea6b4d2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x5608088472d0 .functor OR 1, L_0x560808847460, L_0x7f3ea6b4d2e8, C4<0>, C4<0>;
+v0x560808836240_0 .net "A", 3 0, v0x56080883b1b0_0;  1 drivers
+v0x560808836340_0 .net "B", 3 0, v0x56080883b2a0_0;  1 drivers
+v0x560808836420_0 .net "S0", 4 0, L_0x56080883f1d0;  1 drivers
+v0x5608088364e0_0 .net "S1", 4 0, L_0x560808842710;  1 drivers
+v0x5608088365c0_0 .net "S2", 4 0, L_0x560808845d90;  1 drivers
+v0x5608088366f0_0 .net "Y", 7 0, L_0x560808846dd0;  alias, 1 drivers
+v0x5608088367d0_0 .net *"_ivl_1", 0 0, L_0x56080883b470;  1 drivers
+v0x5608088368b0_0 .net *"_ivl_10", 0 0, L_0x56080883b810;  1 drivers
+v0x560808836990_0 .net *"_ivl_101", 0 0, L_0x560808842a60;  1 drivers
+v0x560808836a70_0 .net *"_ivl_102", 0 0, L_0x56080883f790;  1 drivers
+v0x560808836b50_0 .net *"_ivl_105", 0 0, L_0x560808842c10;  1 drivers
+v0x560808836c30_0 .net *"_ivl_107", 0 0, L_0x560808842cb0;  1 drivers
+v0x560808836d10_0 .net *"_ivl_108", 0 0, L_0x560808842ec0;  1 drivers
+v0x560808836df0_0 .net *"_ivl_111", 0 0, L_0x560808842fc0;  1 drivers
+v0x560808836ed0_0 .net *"_ivl_113", 0 0, L_0x5608088430b0;  1 drivers
+v0x560808836fb0_0 .net *"_ivl_114", 0 0, L_0x5608088435d0;  1 drivers
+v0x560808837090_0 .net *"_ivl_118", 0 0, L_0x560808843690;  1 drivers
+v0x560808837170_0 .net *"_ivl_12", 0 0, L_0x56080883b900;  1 drivers
+v0x560808837250_0 .net *"_ivl_120", 0 0, L_0x5608088438c0;  1 drivers
+v0x560808837330_0 .net *"_ivl_13", 0 0, L_0x56080883ba20;  1 drivers
+v0x560808837410_0 .net *"_ivl_130", 0 0, L_0x560808845900;  1 drivers
+v0x5608088374f0_0 .net *"_ivl_133", 0 0, L_0x560808845f60;  1 drivers
+v0x5608088375d0_0 .net/2u *"_ivl_134", 0 0, L_0x7f3ea6b4d138;  1 drivers
+v0x5608088376b0_0 .net *"_ivl_136", 0 0, L_0x560808846160;  1 drivers
+v0x560808837790_0 .net *"_ivl_139", 0 0, L_0x5608088461d0;  1 drivers
+v0x560808837870_0 .net/2u *"_ivl_140", 0 0, L_0x7f3ea6b4d180;  1 drivers
+v0x560808837950_0 .net *"_ivl_142", 0 0, L_0x560808846310;  1 drivers
+v0x560808837a30_0 .net *"_ivl_145", 0 0, L_0x560808845ec0;  1 drivers
+v0x560808837b10_0 .net/2u *"_ivl_146", 0 0, L_0x7f3ea6b4d1c8;  1 drivers
+v0x560808837bf0_0 .net *"_ivl_148", 0 0, L_0x560808846690;  1 drivers
+v0x560808837cd0_0 .net *"_ivl_151", 0 0, L_0x560808846700;  1 drivers
+v0x560808837db0_0 .net/2u *"_ivl_152", 0 0, L_0x7f3ea6b4d210;  1 drivers
+v0x560808837e90_0 .net *"_ivl_154", 0 0, L_0x560808846840;  1 drivers
+v0x560808838180_0 .net *"_ivl_157", 0 0, L_0x560808846970;  1 drivers
+v0x560808838260_0 .net/2u *"_ivl_158", 0 0, L_0x7f3ea6b4d258;  1 drivers
+v0x560808838340_0 .net *"_ivl_16", 0 0, L_0x56080883ba90;  1 drivers
+v0x560808838420_0 .net *"_ivl_160", 0 0, L_0x560808846c70;  1 drivers
+v0x560808838500_0 .net *"_ivl_163", 0 0, L_0x560808846ce0;  1 drivers
+v0x5608088385e0_0 .net/2u *"_ivl_164", 0 0, L_0x7f3ea6b4d2a0;  1 drivers
+v0x5608088386c0_0 .net *"_ivl_166", 0 0, L_0x5608088472d0;  1 drivers
+v0x5608088387a0_0 .net *"_ivl_170", 0 0, L_0x560808847460;  1 drivers
+v0x560808838880_0 .net/2u *"_ivl_171", 0 0, L_0x7f3ea6b4d2e8;  1 drivers
+v0x560808838960_0 .net *"_ivl_18", 0 0, L_0x56080883bb80;  1 drivers
+v0x560808838a40_0 .net *"_ivl_19", 0 0, L_0x56080883bc60;  1 drivers
+v0x560808838b20_0 .net *"_ivl_22", 0 0, L_0x56080883bd00;  1 drivers
+v0x560808838c00_0 .net *"_ivl_24", 0 0, L_0x56080883bda0;  1 drivers
+v0x560808838ce0_0 .net *"_ivl_25", 0 0, L_0x56080883c0c0;  1 drivers
+v0x560808838dc0_0 .net/2u *"_ivl_28", 0 0, L_0x7f3ea6b4d018;  1 drivers
+v0x560808838ea0_0 .net *"_ivl_30", 0 0, L_0x56080883c1d0;  1 drivers
+v0x560808838f80_0 .net *"_ivl_33", 0 0, L_0x56080883c280;  1 drivers
+v0x560808839060_0 .net *"_ivl_35", 0 0, L_0x56080883c3d0;  1 drivers
+v0x560808839140_0 .net *"_ivl_36", 0 0, L_0x56080883c470;  1 drivers
+v0x560808839220_0 .net *"_ivl_39", 0 0, L_0x56080883c4e0;  1 drivers
+v0x560808839300_0 .net *"_ivl_4", 0 0, L_0x56080883b570;  1 drivers
+v0x5608088393e0_0 .net *"_ivl_41", 0 0, L_0x56080883c640;  1 drivers
+v0x5608088394c0_0 .net *"_ivl_42", 0 0, L_0x56080883c730;  1 drivers
+v0x5608088395a0_0 .net *"_ivl_45", 0 0, L_0x56080883c7f0;  1 drivers
+v0x560808839680_0 .net *"_ivl_47", 0 0, L_0x56080883c960;  1 drivers
+v0x560808839760_0 .net *"_ivl_48", 0 0, L_0x56080883c5d0;  1 drivers
+v0x560808839840_0 .net *"_ivl_52", 0 0, L_0x56080883cd10;  1 drivers
+v0x560808839920_0 .net *"_ivl_54", 0 0, L_0x56080883ce00;  1 drivers
+v0x560808839a00_0 .net *"_ivl_6", 0 0, L_0x56080883b660;  1 drivers
+v0x560808839ae0_0 .net *"_ivl_62", 0 0, L_0x56080883ef10;  1 drivers
+v0x560808839bc0_0 .net *"_ivl_65", 0 0, L_0x56080883f360;  1 drivers
+v0x560808839ca0_0 .net *"_ivl_67", 0 0, L_0x56080883cef0;  1 drivers
+v0x56080883a190_0 .net *"_ivl_68", 0 0, L_0x56080883f4b0;  1 drivers
+v0x56080883a270_0 .net *"_ivl_7", 0 0, L_0x56080883b7a0;  1 drivers
+v0x56080883a350_0 .net *"_ivl_71", 0 0, L_0x56080883f520;  1 drivers
+v0x56080883a430_0 .net *"_ivl_73", 0 0, L_0x56080883f680;  1 drivers
+v0x56080883a510_0 .net *"_ivl_74", 0 0, L_0x56080883f720;  1 drivers
+v0x56080883a5f0_0 .net *"_ivl_77", 0 0, L_0x56080883f800;  1 drivers
+v0x56080883a6d0_0 .net *"_ivl_79", 0 0, L_0x56080883f9c0;  1 drivers
+v0x56080883a7b0_0 .net *"_ivl_80", 0 0, L_0x56080883fd70;  1 drivers
+v0x56080883a890_0 .net *"_ivl_84", 0 0, L_0x56080883fe30;  1 drivers
+v0x56080883a970_0 .net *"_ivl_86", 0 0, L_0x56080883ff20;  1 drivers
+v0x56080883aa50_0 .net *"_ivl_96", 0 0, L_0x5608088423d0;  1 drivers
+v0x56080883ab30_0 .net *"_ivl_99", 0 0, L_0x5608088429c0;  1 drivers
+v0x56080883ac10_0 .net "a0", 3 0, L_0x56080883ca50;  1 drivers
+v0x56080883acd0_0 .net "a1", 3 0, L_0x56080883fab0;  1 drivers
+v0x56080883ada0_0 .net "a2", 3 0, L_0x560808842da0;  1 drivers
+v0x56080883ae70_0 .net "b0", 3 0, L_0x56080883bee0;  1 drivers
+v0x56080883af40_0 .net "overflow0", 0 0, L_0x56080883f020;  1 drivers
+v0x56080883b010_0 .net "overflow1", 0 0, L_0x5608088424e0;  1 drivers
+v0x56080883b0e0_0 .net "overflow2", 0 0, L_0x560808845a10;  1 drivers
+L_0x56080883b570 .part v0x56080883b1b0_0, 0, 1;
+L_0x56080883b660 .part v0x56080883b2a0_0, 0, 1;
+L_0x56080883b810 .part v0x56080883b1b0_0, 1, 1;
+L_0x56080883b900 .part v0x56080883b2a0_0, 0, 1;
+L_0x56080883ba90 .part v0x56080883b1b0_0, 2, 1;
+L_0x56080883bb80 .part v0x56080883b2a0_0, 0, 1;
+L_0x56080883bd00 .part v0x56080883b1b0_0, 3, 1;
+L_0x56080883bda0 .part v0x56080883b2a0_0, 0, 1;
+L_0x56080883bee0 .concat8 [ 1 1 1 1], L_0x56080883b7a0, L_0x56080883ba20, L_0x56080883bc60, L_0x56080883c0c0;
+L_0x56080883c280 .part v0x56080883b1b0_0, 0, 1;
+L_0x56080883c3d0 .part v0x56080883b2a0_0, 1, 1;
+L_0x56080883c4e0 .part v0x56080883b1b0_0, 1, 1;
+L_0x56080883c640 .part v0x56080883b2a0_0, 1, 1;
+L_0x56080883c7f0 .part v0x56080883b1b0_0, 2, 1;
+L_0x56080883c960 .part v0x56080883b2a0_0, 1, 1;
+L_0x56080883ca50 .concat8 [ 1 1 1 1], L_0x56080883c1d0, L_0x56080883c470, L_0x56080883c730, L_0x56080883c5d0;
+L_0x56080883cd10 .part v0x56080883b1b0_0, 3, 1;
+L_0x56080883ce00 .part v0x56080883b2a0_0, 1, 1;
+L_0x56080883f1d0 .concat8 [ 4 1 0 0], L_0x56080883ef80, L_0x56080883e990;
+L_0x56080883f360 .part v0x56080883b1b0_0, 0, 1;
+L_0x56080883cef0 .part v0x56080883b2a0_0, 2, 1;
+L_0x56080883f520 .part v0x56080883b1b0_0, 1, 1;
+L_0x56080883f680 .part v0x56080883b2a0_0, 2, 1;
+L_0x56080883f800 .part v0x56080883b1b0_0, 2, 1;
+L_0x56080883f9c0 .part v0x56080883b2a0_0, 2, 1;
+L_0x56080883fab0 .concat8 [ 1 1 1 1], L_0x56080883ef10, L_0x56080883f4b0, L_0x56080883f720, L_0x56080883fd70;
+L_0x56080883fe30 .part v0x56080883b1b0_0, 3, 1;
+L_0x56080883ff20 .part v0x56080883b2a0_0, 2, 1;
+L_0x560808842670 .part L_0x56080883f1d0, 1, 4;
+L_0x560808842710 .concat8 [ 4 1 0 0], L_0x560808842440, L_0x560808841dc0;
+L_0x5608088429c0 .part v0x56080883b1b0_0, 0, 1;
+L_0x560808842a60 .part v0x56080883b2a0_0, 3, 1;
+L_0x560808842c10 .part v0x56080883b1b0_0, 1, 1;
+L_0x560808842cb0 .part v0x56080883b2a0_0, 3, 1;
+L_0x560808842fc0 .part v0x56080883b1b0_0, 2, 1;
+L_0x5608088430b0 .part v0x56080883b2a0_0, 3, 1;
+L_0x560808842da0 .concat8 [ 1 1 1 1], L_0x5608088423d0, L_0x56080883f790, L_0x560808842ec0, L_0x5608088435d0;
+L_0x560808843690 .part v0x56080883b1b0_0, 3, 1;
+L_0x5608088438c0 .part v0x56080883b2a0_0, 3, 1;
+L_0x560808845ba0 .part L_0x560808842710, 1, 4;
+L_0x560808845d90 .concat8 [ 4 1 0 0], L_0x560808845970, L_0x560808845330;
+L_0x560808845f60 .part L_0x56080883f1d0, 0, 1;
+L_0x5608088461d0 .part L_0x560808842710, 0, 1;
+L_0x560808845ec0 .part L_0x560808845d90, 0, 1;
+L_0x560808846700 .part L_0x560808845d90, 1, 1;
+L_0x560808846970 .part L_0x560808845d90, 2, 1;
+L_0x560808846ce0 .part L_0x560808845d90, 3, 1;
+LS_0x560808846dd0_0_0 .concat8 [ 1 1 1 1], L_0x56080883b470, L_0x560808845900, L_0x560808846160, L_0x560808846310;
+LS_0x560808846dd0_0_4 .concat8 [ 1 1 1 1], L_0x560808846690, L_0x560808846840, L_0x560808846c70, L_0x5608088472d0;
+L_0x560808846dd0 .concat8 [ 4 4 0 0], LS_0x560808846dd0_0_0, LS_0x560808846dd0_0_4;
+L_0x560808847460 .part L_0x560808845d90, 4, 1;
+S_0x5608087fbca0 .scope module, "add0" "addition" 3 26, 4 1 0, S_0x560808804330;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /INPUT 1 "CarryIN";
+    .port_info 3 /OUTPUT 4 "Y";
+    .port_info 4 /OUTPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflow";
+L_0x56080883f020 .functor XOR 1, L_0x56080883f090, L_0x56080883e990, C4<0>, C4<0>;
+v0x560808829b90_0 .net "A", 3 0, L_0x56080883ca50;  alias, 1 drivers
+v0x560808829c70_0 .net "B", 3 0, L_0x56080883bee0;  alias, 1 drivers
+v0x560808829d50_0 .net "Carry4", 2 0, L_0x56080883e400;  1 drivers
+L_0x7f3ea6b4d060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x560808829e10_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d060;  1 drivers
+v0x560808829f00_0 .net "CarryOUT", 0 0, L_0x56080883e990;  1 drivers
+v0x560808829ff0_0 .net "Y", 3 0, L_0x56080883ef80;  1 drivers
+v0x56080882a0b0_0 .net *"_ivl_39", 0 0, L_0x56080883f090;  1 drivers
+v0x56080882a190_0 .net "overflow", 0 0, L_0x56080883f020;  alias, 1 drivers
+L_0x56080883d300 .part L_0x56080883ca50, 0, 1;
+L_0x56080883d3a0 .part L_0x56080883bee0, 0, 1;
+L_0x56080883d830 .part L_0x56080883ca50, 1, 1;
+L_0x56080883d9f0 .part L_0x56080883bee0, 1, 1;
+L_0x56080883dbb0 .part L_0x56080883e400, 0, 1;
+L_0x56080883dfe0 .part L_0x56080883ca50, 2, 1;
+L_0x56080883e150 .part L_0x56080883bee0, 2, 1;
+L_0x56080883e280 .part L_0x56080883e400, 1, 1;
+L_0x56080883e400 .concat8 [ 1 1 1 0], L_0x56080883d290, L_0x56080883d7c0, L_0x56080883df50;
+L_0x56080883ea90 .part L_0x56080883ca50, 3, 1;
+L_0x56080883ec20 .part L_0x56080883bee0, 3, 1;
+L_0x56080883ed50 .part L_0x56080883e400, 2, 1;
+L_0x56080883ef80 .concat8 [ 1 1 1 1], L_0x56080883d220, L_0x56080883d700, L_0x56080883dec0, L_0x56080883e8b0;
+L_0x56080883f090 .part L_0x56080883e400, 2, 1;
+S_0x5608087fa200 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608087fbca0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x56080883d290 .functor OR 1, L_0x56080883cf90, L_0x56080883d160, C4<0>, C4<0>;
+v0x560808825840_0 .net "A", 0 0, L_0x56080883d300;  1 drivers
+v0x560808825900_0 .net "B", 0 0, L_0x56080883d3a0;  1 drivers
+v0x5608088259d0_0 .net "Carry", 0 0, L_0x7f3ea6b4d060;  alias, 1 drivers
+v0x560808825ad0_0 .net "CarryO", 0 0, L_0x56080883d290;  1 drivers
+v0x560808825b70_0 .net "Sum", 0 0, L_0x56080883d220;  1 drivers
+v0x560808825c60_0 .net "and1", 0 0, L_0x56080883cf90;  1 drivers
+v0x560808825d30_0 .net "and2", 0 0, L_0x56080883d160;  1 drivers
+v0x560808825e00_0 .net "xor1", 0 0, L_0x56080883d0f0;  1 drivers
+S_0x5608087f1eb0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x5608087fa200;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883cf90 .functor AND 1, L_0x56080883d300, L_0x56080883d3a0, C4<1>, C4<1>;
+L_0x56080883d0f0 .functor XOR 1, L_0x56080883d300, L_0x56080883d3a0, C4<0>, C4<0>;
+v0x56080880a2e0_0 .net "A", 0 0, L_0x56080883d300;  alias, 1 drivers
+v0x560808809740_0 .net "B", 0 0, L_0x56080883d3a0;  alias, 1 drivers
+v0x560808808a00_0 .net "Carry", 0 0, L_0x56080883cf90;  alias, 1 drivers
+v0x56080878a680_0 .net "Sum", 0 0, L_0x56080883d0f0;  alias, 1 drivers
+S_0x5608088252c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x5608087fa200;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883d160 .functor AND 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<1>, C4<1>;
+L_0x56080883d220 .functor XOR 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<0>, C4<0>;
+v0x5608088254c0_0 .net "A", 0 0, L_0x56080883d0f0;  alias, 1 drivers
+v0x560808825560_0 .net "B", 0 0, L_0x7f3ea6b4d060;  alias, 1 drivers
+v0x560808825600_0 .net "Carry", 0 0, L_0x56080883d160;  alias, 1 drivers
+v0x5608088256d0_0 .net "Sum", 0 0, L_0x56080883d220;  alias, 1 drivers
+S_0x560808825ef0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608087fbca0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x56080883d7c0 .functor OR 1, L_0x56080883d4d0, L_0x56080883d5b0, C4<0>, C4<0>;
+v0x560808826c70_0 .net "A", 0 0, L_0x56080883d830;  1 drivers
+v0x560808826d30_0 .net "B", 0 0, L_0x56080883d9f0;  1 drivers
+v0x560808826e00_0 .net "Carry", 0 0, L_0x56080883dbb0;  1 drivers
+v0x560808826f00_0 .net "CarryO", 0 0, L_0x56080883d7c0;  1 drivers
+v0x560808826fa0_0 .net "Sum", 0 0, L_0x56080883d700;  1 drivers
+v0x560808827090_0 .net "and1", 0 0, L_0x56080883d4d0;  1 drivers
+v0x560808827160_0 .net "and2", 0 0, L_0x56080883d5b0;  1 drivers
+v0x560808827230_0 .net "xor1", 0 0, L_0x56080883d540;  1 drivers
+S_0x5608088260d0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808825ef0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883d4d0 .functor AND 1, L_0x56080883d830, L_0x56080883d9f0, C4<1>, C4<1>;
+L_0x56080883d540 .functor XOR 1, L_0x56080883d830, L_0x56080883d9f0, C4<0>, C4<0>;
+v0x5608088262e0_0 .net "A", 0 0, L_0x56080883d830;  alias, 1 drivers
+v0x5608088263c0_0 .net "B", 0 0, L_0x56080883d9f0;  alias, 1 drivers
+v0x560808826480_0 .net "Carry", 0 0, L_0x56080883d4d0;  alias, 1 drivers
+v0x560808826550_0 .net "Sum", 0 0, L_0x56080883d540;  alias, 1 drivers
+S_0x5608088266c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808825ef0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883d5b0 .functor AND 1, L_0x56080883d540, L_0x56080883dbb0, C4<1>, C4<1>;
+L_0x56080883d700 .functor XOR 1, L_0x56080883d540, L_0x56080883dbb0, C4<0>, C4<0>;
+v0x5608088268c0_0 .net "A", 0 0, L_0x56080883d540;  alias, 1 drivers
+v0x560808826990_0 .net "B", 0 0, L_0x56080883dbb0;  alias, 1 drivers
+v0x560808826a30_0 .net "Carry", 0 0, L_0x56080883d5b0;  alias, 1 drivers
+v0x560808826b00_0 .net "Sum", 0 0, L_0x56080883d700;  alias, 1 drivers
+S_0x560808827320 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608087fbca0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x56080883df50 .functor OR 1, L_0x56080883dce0, L_0x56080883ddc0, C4<0>, C4<0>;
+v0x5608088280b0_0 .net "A", 0 0, L_0x56080883dfe0;  1 drivers
+v0x560808828170_0 .net "B", 0 0, L_0x56080883e150;  1 drivers
+v0x560808828240_0 .net "Carry", 0 0, L_0x56080883e280;  1 drivers
+v0x560808828340_0 .net "CarryO", 0 0, L_0x56080883df50;  1 drivers
+v0x5608088283e0_0 .net "Sum", 0 0, L_0x56080883dec0;  1 drivers
+v0x5608088284d0_0 .net "and1", 0 0, L_0x56080883dce0;  1 drivers
+v0x5608088285a0_0 .net "and2", 0 0, L_0x56080883ddc0;  1 drivers
+v0x560808828670_0 .net "xor1", 0 0, L_0x56080883dd50;  1 drivers
+S_0x560808827530 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808827320;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883dce0 .functor AND 1, L_0x56080883dfe0, L_0x56080883e150, C4<1>, C4<1>;
+L_0x56080883dd50 .functor XOR 1, L_0x56080883dfe0, L_0x56080883e150, C4<0>, C4<0>;
+v0x560808827740_0 .net "A", 0 0, L_0x56080883dfe0;  alias, 1 drivers
+v0x560808827800_0 .net "B", 0 0, L_0x56080883e150;  alias, 1 drivers
+v0x5608088278c0_0 .net "Carry", 0 0, L_0x56080883dce0;  alias, 1 drivers
+v0x560808827990_0 .net "Sum", 0 0, L_0x56080883dd50;  alias, 1 drivers
+S_0x560808827b00 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808827320;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883ddc0 .functor AND 1, L_0x56080883dd50, L_0x56080883e280, C4<1>, C4<1>;
+L_0x56080883dec0 .functor XOR 1, L_0x56080883dd50, L_0x56080883e280, C4<0>, C4<0>;
+v0x560808827d00_0 .net "A", 0 0, L_0x56080883dd50;  alias, 1 drivers
+v0x560808827dd0_0 .net "B", 0 0, L_0x56080883e280;  alias, 1 drivers
+v0x560808827e70_0 .net "Carry", 0 0, L_0x56080883ddc0;  alias, 1 drivers
+v0x560808827f40_0 .net "Sum", 0 0, L_0x56080883dec0;  alias, 1 drivers
+S_0x560808828760 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608087fbca0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x56080883e990 .functor OR 1, L_0x56080883e4f0, L_0x56080883e720, C4<0>, C4<0>;
+v0x5608088294e0_0 .net "A", 0 0, L_0x56080883ea90;  1 drivers
+v0x5608088295a0_0 .net "B", 0 0, L_0x56080883ec20;  1 drivers
+v0x560808829670_0 .net "Carry", 0 0, L_0x56080883ed50;  1 drivers
+v0x560808829770_0 .net "CarryO", 0 0, L_0x56080883e990;  alias, 1 drivers
+v0x560808829810_0 .net "Sum", 0 0, L_0x56080883e8b0;  1 drivers
+v0x560808829900_0 .net "and1", 0 0, L_0x56080883e4f0;  1 drivers
+v0x5608088299d0_0 .net "and2", 0 0, L_0x56080883e720;  1 drivers
+v0x560808829aa0_0 .net "xor1", 0 0, L_0x56080883e690;  1 drivers
+S_0x560808828940 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808828760;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883e4f0 .functor AND 1, L_0x56080883ea90, L_0x56080883ec20, C4<1>, C4<1>;
+L_0x56080883e690 .functor XOR 1, L_0x56080883ea90, L_0x56080883ec20, C4<0>, C4<0>;
+v0x560808828b50_0 .net "A", 0 0, L_0x56080883ea90;  alias, 1 drivers
+v0x560808828c30_0 .net "B", 0 0, L_0x56080883ec20;  alias, 1 drivers
+v0x560808828cf0_0 .net "Carry", 0 0, L_0x56080883e4f0;  alias, 1 drivers
+v0x560808828dc0_0 .net "Sum", 0 0, L_0x56080883e690;  alias, 1 drivers
+S_0x560808828f30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808828760;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x56080883e720 .functor AND 1, L_0x56080883e690, L_0x56080883ed50, C4<1>, C4<1>;
+L_0x56080883e8b0 .functor XOR 1, L_0x56080883e690, L_0x56080883ed50, C4<0>, C4<0>;
+v0x560808829130_0 .net "A", 0 0, L_0x56080883e690;  alias, 1 drivers
+v0x560808829200_0 .net "B", 0 0, L_0x56080883ed50;  alias, 1 drivers
+v0x5608088292a0_0 .net "Carry", 0 0, L_0x56080883e720;  alias, 1 drivers
+v0x560808829370_0 .net "Sum", 0 0, L_0x56080883e8b0;  alias, 1 drivers
+S_0x56080882a310 .scope module, "add1" "addition" 3 42, 4 1 0, S_0x560808804330;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /INPUT 1 "CarryIN";
+    .port_info 3 /OUTPUT 4 "Y";
+    .port_info 4 /OUTPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflow";
+L_0x5608088424e0 .functor XOR 1, L_0x560808842550, L_0x560808841dc0, C4<0>, C4<0>;
+v0x56080882fa20_0 .net "A", 3 0, L_0x56080883fab0;  alias, 1 drivers
+v0x56080882fb00_0 .net "B", 3 0, L_0x560808842670;  1 drivers
+v0x56080882fbe0_0 .net "Carry4", 2 0, L_0x560808841830;  1 drivers
+L_0x7f3ea6b4d0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x56080882fca0_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0a8;  1 drivers
+v0x56080882fd90_0 .net "CarryOUT", 0 0, L_0x560808841dc0;  1 drivers
+v0x56080882fe80_0 .net "Y", 3 0, L_0x560808842440;  1 drivers
+v0x56080882ff40_0 .net *"_ivl_39", 0 0, L_0x560808842550;  1 drivers
+v0x560808830020_0 .net "overflow", 0 0, L_0x5608088424e0;  alias, 1 drivers
+L_0x560808840590 .part L_0x56080883fab0, 0, 1;
+L_0x5608088406c0 .part L_0x560808842670, 0, 1;
+L_0x560808840bf0 .part L_0x56080883fab0, 1, 1;
+L_0x560808840db0 .part L_0x560808842670, 1, 1;
+L_0x560808840ee0 .part L_0x560808841830, 0, 1;
+L_0x560808841410 .part L_0x56080883fab0, 2, 1;
+L_0x560808841580 .part L_0x560808842670, 2, 1;
+L_0x5608088416b0 .part L_0x560808841830, 1, 1;
+L_0x560808841830 .concat8 [ 1 1 1 0], L_0x560808840520, L_0x560808840b60, L_0x560808841380;
+L_0x560808841ec0 .part L_0x56080883fab0, 3, 1;
+L_0x560808842050 .part L_0x560808842670, 3, 1;
+L_0x560808842210 .part L_0x560808841830, 2, 1;
+L_0x560808842440 .concat8 [ 1 1 1 1], L_0x560808840420, L_0x560808840a80, L_0x5608088412a0, L_0x560808841ce0;
+L_0x560808842550 .part L_0x560808841830, 2, 1;
+S_0x56080882a5b0 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x56080882a310;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x560808840520 .functor OR 1, L_0x560808840100, L_0x5608088402d0, C4<0>, C4<0>;
+v0x56080882b430_0 .net "A", 0 0, L_0x560808840590;  1 drivers
+v0x56080882b4f0_0 .net "B", 0 0, L_0x5608088406c0;  1 drivers
+v0x56080882b5c0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0a8;  alias, 1 drivers
+v0x56080882b6c0_0 .net "CarryO", 0 0, L_0x560808840520;  1 drivers
+v0x56080882b760_0 .net "Sum", 0 0, L_0x560808840420;  1 drivers
+v0x56080882b850_0 .net "and1", 0 0, L_0x560808840100;  1 drivers
+v0x56080882b920_0 .net "and2", 0 0, L_0x5608088402d0;  1 drivers
+v0x56080882b9f0_0 .net "xor1", 0 0, L_0x560808840260;  1 drivers
+S_0x56080882a790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882a5b0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808840100 .functor AND 1, L_0x560808840590, L_0x5608088406c0, C4<1>, C4<1>;
+L_0x560808840260 .functor XOR 1, L_0x560808840590, L_0x5608088406c0, C4<0>, C4<0>;
+v0x56080882aa30_0 .net "A", 0 0, L_0x560808840590;  alias, 1 drivers
+v0x56080882ab10_0 .net "B", 0 0, L_0x5608088406c0;  alias, 1 drivers
+v0x56080882abd0_0 .net "Carry", 0 0, L_0x560808840100;  alias, 1 drivers
+v0x56080882aca0_0 .net "Sum", 0 0, L_0x560808840260;  alias, 1 drivers
+S_0x56080882ae10 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882a5b0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x5608088402d0 .functor AND 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<1>, C4<1>;
+L_0x560808840420 .functor XOR 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<0>, C4<0>;
+v0x56080882b080_0 .net "A", 0 0, L_0x560808840260;  alias, 1 drivers
+v0x56080882b150_0 .net "B", 0 0, L_0x7f3ea6b4d0a8;  alias, 1 drivers
+v0x56080882b1f0_0 .net "Carry", 0 0, L_0x5608088402d0;  alias, 1 drivers
+v0x56080882b2c0_0 .net "Sum", 0 0, L_0x560808840420;  alias, 1 drivers
+S_0x56080882bae0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x56080882a310;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x560808840b60 .functor OR 1, L_0x5608088407f0, L_0x5608088408f0, C4<0>, C4<0>;
+v0x56080882c940_0 .net "A", 0 0, L_0x560808840bf0;  1 drivers
+v0x56080882ca00_0 .net "B", 0 0, L_0x560808840db0;  1 drivers
+v0x56080882cad0_0 .net "Carry", 0 0, L_0x560808840ee0;  1 drivers
+v0x56080882cbd0_0 .net "CarryO", 0 0, L_0x560808840b60;  1 drivers
+v0x56080882cc70_0 .net "Sum", 0 0, L_0x560808840a80;  1 drivers
+v0x56080882cd60_0 .net "and1", 0 0, L_0x5608088407f0;  1 drivers
+v0x56080882ce30_0 .net "and2", 0 0, L_0x5608088408f0;  1 drivers
+v0x56080882cf00_0 .net "xor1", 0 0, L_0x560808840860;  1 drivers
+S_0x56080882bcc0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882bae0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x5608088407f0 .functor AND 1, L_0x560808840bf0, L_0x560808840db0, C4<1>, C4<1>;
+L_0x560808840860 .functor XOR 1, L_0x560808840bf0, L_0x560808840db0, C4<0>, C4<0>;
+v0x56080882bf40_0 .net "A", 0 0, L_0x560808840bf0;  alias, 1 drivers
+v0x56080882c020_0 .net "B", 0 0, L_0x560808840db0;  alias, 1 drivers
+v0x56080882c0e0_0 .net "Carry", 0 0, L_0x5608088407f0;  alias, 1 drivers
+v0x56080882c1b0_0 .net "Sum", 0 0, L_0x560808840860;  alias, 1 drivers
+S_0x56080882c320 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882bae0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x5608088408f0 .functor AND 1, L_0x560808840860, L_0x560808840ee0, C4<1>, C4<1>;
+L_0x560808840a80 .functor XOR 1, L_0x560808840860, L_0x560808840ee0, C4<0>, C4<0>;
+v0x56080882c590_0 .net "A", 0 0, L_0x560808840860;  alias, 1 drivers
+v0x56080882c660_0 .net "B", 0 0, L_0x560808840ee0;  alias, 1 drivers
+v0x56080882c700_0 .net "Carry", 0 0, L_0x5608088408f0;  alias, 1 drivers
+v0x56080882c7d0_0 .net "Sum", 0 0, L_0x560808840a80;  alias, 1 drivers
+S_0x56080882cff0 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x56080882a310;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x560808841380 .functor OR 1, L_0x560808841010, L_0x560808841110, C4<0>, C4<0>;
+v0x56080882de60_0 .net "A", 0 0, L_0x560808841410;  1 drivers
+v0x56080882df20_0 .net "B", 0 0, L_0x560808841580;  1 drivers
+v0x56080882dff0_0 .net "Carry", 0 0, L_0x5608088416b0;  1 drivers
+v0x56080882e0f0_0 .net "CarryO", 0 0, L_0x560808841380;  1 drivers
+v0x56080882e190_0 .net "Sum", 0 0, L_0x5608088412a0;  1 drivers
+v0x56080882e280_0 .net "and1", 0 0, L_0x560808841010;  1 drivers
+v0x56080882e350_0 .net "and2", 0 0, L_0x560808841110;  1 drivers
+v0x56080882e420_0 .net "xor1", 0 0, L_0x560808841080;  1 drivers
+S_0x56080882d200 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882cff0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808841010 .functor AND 1, L_0x560808841410, L_0x560808841580, C4<1>, C4<1>;
+L_0x560808841080 .functor XOR 1, L_0x560808841410, L_0x560808841580, C4<0>, C4<0>;
+v0x56080882d480_0 .net "A", 0 0, L_0x560808841410;  alias, 1 drivers
+v0x56080882d540_0 .net "B", 0 0, L_0x560808841580;  alias, 1 drivers
+v0x56080882d600_0 .net "Carry", 0 0, L_0x560808841010;  alias, 1 drivers
+v0x56080882d6d0_0 .net "Sum", 0 0, L_0x560808841080;  alias, 1 drivers
+S_0x56080882d840 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882cff0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808841110 .functor AND 1, L_0x560808841080, L_0x5608088416b0, C4<1>, C4<1>;
+L_0x5608088412a0 .functor XOR 1, L_0x560808841080, L_0x5608088416b0, C4<0>, C4<0>;
+v0x56080882dab0_0 .net "A", 0 0, L_0x560808841080;  alias, 1 drivers
+v0x56080882db80_0 .net "B", 0 0, L_0x5608088416b0;  alias, 1 drivers
+v0x56080882dc20_0 .net "Carry", 0 0, L_0x560808841110;  alias, 1 drivers
+v0x56080882dcf0_0 .net "Sum", 0 0, L_0x5608088412a0;  alias, 1 drivers
+S_0x56080882e510 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x56080882a310;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x560808841dc0 .functor OR 1, L_0x560808841920, L_0x560808841b50, C4<0>, C4<0>;
+v0x56080882f370_0 .net "A", 0 0, L_0x560808841ec0;  1 drivers
+v0x56080882f430_0 .net "B", 0 0, L_0x560808842050;  1 drivers
+v0x56080882f500_0 .net "Carry", 0 0, L_0x560808842210;  1 drivers
+v0x56080882f600_0 .net "CarryO", 0 0, L_0x560808841dc0;  alias, 1 drivers
+v0x56080882f6a0_0 .net "Sum", 0 0, L_0x560808841ce0;  1 drivers
+v0x56080882f790_0 .net "and1", 0 0, L_0x560808841920;  1 drivers
+v0x56080882f860_0 .net "and2", 0 0, L_0x560808841b50;  1 drivers
+v0x56080882f930_0 .net "xor1", 0 0, L_0x560808841ac0;  1 drivers
+S_0x56080882e6f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882e510;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808841920 .functor AND 1, L_0x560808841ec0, L_0x560808842050, C4<1>, C4<1>;
+L_0x560808841ac0 .functor XOR 1, L_0x560808841ec0, L_0x560808842050, C4<0>, C4<0>;
+v0x56080882e970_0 .net "A", 0 0, L_0x560808841ec0;  alias, 1 drivers
+v0x56080882ea50_0 .net "B", 0 0, L_0x560808842050;  alias, 1 drivers
+v0x56080882eb10_0 .net "Carry", 0 0, L_0x560808841920;  alias, 1 drivers
+v0x56080882ebe0_0 .net "Sum", 0 0, L_0x560808841ac0;  alias, 1 drivers
+S_0x56080882ed50 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882e510;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808841b50 .functor AND 1, L_0x560808841ac0, L_0x560808842210, C4<1>, C4<1>;
+L_0x560808841ce0 .functor XOR 1, L_0x560808841ac0, L_0x560808842210, C4<0>, C4<0>;
+v0x56080882efc0_0 .net "A", 0 0, L_0x560808841ac0;  alias, 1 drivers
+v0x56080882f090_0 .net "B", 0 0, L_0x560808842210;  alias, 1 drivers
+v0x56080882f130_0 .net "Carry", 0 0, L_0x560808841b50;  alias, 1 drivers
+v0x56080882f200_0 .net "Sum", 0 0, L_0x560808841ce0;  alias, 1 drivers
+S_0x5608088301a0 .scope module, "add2" "addition" 3 58, 4 1 0, S_0x560808804330;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /INPUT 1 "CarryIN";
+    .port_info 3 /OUTPUT 4 "Y";
+    .port_info 4 /OUTPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflow";
+L_0x560808845a10 .functor XOR 1, L_0x560808845a80, L_0x560808845330, C4<0>, C4<0>;
+v0x560808835ac0_0 .net "A", 3 0, L_0x560808842da0;  alias, 1 drivers
+v0x560808835ba0_0 .net "B", 3 0, L_0x560808845ba0;  1 drivers
+v0x560808835c80_0 .net "Carry4", 2 0, L_0x560808844e60;  1 drivers
+L_0x7f3ea6b4d0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x560808835d40_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0f0;  1 drivers
+v0x560808835e30_0 .net "CarryOUT", 0 0, L_0x560808845330;  1 drivers
+v0x560808835f20_0 .net "Y", 3 0, L_0x560808845970;  1 drivers
+v0x560808835fe0_0 .net *"_ivl_39", 0 0, L_0x560808845a80;  1 drivers
+v0x5608088360c0_0 .net "overflow", 0 0, L_0x560808845a10;  alias, 1 drivers
+L_0x560808843e40 .part L_0x560808842da0, 0, 1;
+L_0x560808843f70 .part L_0x560808845ba0, 0, 1;
+L_0x560808844360 .part L_0x560808842da0, 1, 1;
+L_0x560808844520 .part L_0x560808845ba0, 1, 1;
+L_0x560808844650 .part L_0x560808844e60, 0, 1;
+L_0x560808844a40 .part L_0x560808842da0, 2, 1;
+L_0x560808844bb0 .part L_0x560808845ba0, 2, 1;
+L_0x560808844ce0 .part L_0x560808844e60, 1, 1;
+L_0x560808844e60 .concat8 [ 1 1 1 0], L_0x560808843dd0, L_0x5608088442f0, L_0x5608088449d0;
+L_0x5608088453f0 .part L_0x560808842da0, 3, 1;
+L_0x560808845580 .part L_0x560808845ba0, 3, 1;
+L_0x560808845740 .part L_0x560808844e60, 2, 1;
+L_0x560808845970 .concat8 [ 1 1 1 1], L_0x560808843cd0, L_0x560808844280, L_0x560808844960, L_0x560808845270;
+L_0x560808845a80 .part L_0x560808844e60, 2, 1;
+S_0x560808830420 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608088301a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x560808843dd0 .functor OR 1, L_0x5608088439b0, L_0x560808843b80, C4<0>, C4<0>;
+v0x560808831350_0 .net "A", 0 0, L_0x560808843e40;  1 drivers
+v0x560808831410_0 .net "B", 0 0, L_0x560808843f70;  1 drivers
+v0x5608088314e0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0f0;  alias, 1 drivers
+v0x5608088315e0_0 .net "CarryO", 0 0, L_0x560808843dd0;  1 drivers
+v0x560808831680_0 .net "Sum", 0 0, L_0x560808843cd0;  1 drivers
+v0x560808831770_0 .net "and1", 0 0, L_0x5608088439b0;  1 drivers
+v0x560808831840_0 .net "and2", 0 0, L_0x560808843b80;  1 drivers
+v0x560808831910_0 .net "xor1", 0 0, L_0x560808843b10;  1 drivers
+S_0x5608088306b0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808830420;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x5608088439b0 .functor AND 1, L_0x560808843e40, L_0x560808843f70, C4<1>, C4<1>;
+L_0x560808843b10 .functor XOR 1, L_0x560808843e40, L_0x560808843f70, C4<0>, C4<0>;
+v0x560808830950_0 .net "A", 0 0, L_0x560808843e40;  alias, 1 drivers
+v0x560808830a30_0 .net "B", 0 0, L_0x560808843f70;  alias, 1 drivers
+v0x560808830af0_0 .net "Carry", 0 0, L_0x5608088439b0;  alias, 1 drivers
+v0x560808830bc0_0 .net "Sum", 0 0, L_0x560808843b10;  alias, 1 drivers
+S_0x560808830d30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808830420;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808843b80 .functor AND 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<1>, C4<1>;
+L_0x560808843cd0 .functor XOR 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<0>, C4<0>;
+v0x560808830fa0_0 .net "A", 0 0, L_0x560808843b10;  alias, 1 drivers
+v0x560808831070_0 .net "B", 0 0, L_0x7f3ea6b4d0f0;  alias, 1 drivers
+v0x560808831110_0 .net "Carry", 0 0, L_0x560808843b80;  alias, 1 drivers
+v0x5608088311e0_0 .net "Sum", 0 0, L_0x560808843cd0;  alias, 1 drivers
+S_0x560808831a00 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608088301a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x5608088442f0 .functor OR 1, L_0x5608088440a0, L_0x560808844180, C4<0>, C4<0>;
+v0x5608088328e0_0 .net "A", 0 0, L_0x560808844360;  1 drivers
+v0x5608088329a0_0 .net "B", 0 0, L_0x560808844520;  1 drivers
+v0x560808832a70_0 .net "Carry", 0 0, L_0x560808844650;  1 drivers
+v0x560808832b70_0 .net "CarryO", 0 0, L_0x5608088442f0;  1 drivers
+v0x560808832c10_0 .net "Sum", 0 0, L_0x560808844280;  1 drivers
+v0x560808832d00_0 .net "and1", 0 0, L_0x5608088440a0;  1 drivers
+v0x560808832dd0_0 .net "and2", 0 0, L_0x560808844180;  1 drivers
+v0x560808832ea0_0 .net "xor1", 0 0, L_0x560808844110;  1 drivers
+S_0x560808831c60 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808831a00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x5608088440a0 .functor AND 1, L_0x560808844360, L_0x560808844520, C4<1>, C4<1>;
+L_0x560808844110 .functor XOR 1, L_0x560808844360, L_0x560808844520, C4<0>, C4<0>;
+v0x560808831ee0_0 .net "A", 0 0, L_0x560808844360;  alias, 1 drivers
+v0x560808831fc0_0 .net "B", 0 0, L_0x560808844520;  alias, 1 drivers
+v0x560808832080_0 .net "Carry", 0 0, L_0x5608088440a0;  alias, 1 drivers
+v0x560808832150_0 .net "Sum", 0 0, L_0x560808844110;  alias, 1 drivers
+S_0x5608088322c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808831a00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808844180 .functor AND 1, L_0x560808844110, L_0x560808844650, C4<1>, C4<1>;
+L_0x560808844280 .functor XOR 1, L_0x560808844110, L_0x560808844650, C4<0>, C4<0>;
+v0x560808832530_0 .net "A", 0 0, L_0x560808844110;  alias, 1 drivers
+v0x560808832600_0 .net "B", 0 0, L_0x560808844650;  alias, 1 drivers
+v0x5608088326a0_0 .net "Carry", 0 0, L_0x560808844180;  alias, 1 drivers
+v0x560808832770_0 .net "Sum", 0 0, L_0x560808844280;  alias, 1 drivers
+S_0x560808832f90 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608088301a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x5608088449d0 .functor OR 1, L_0x560808844780, L_0x560808844860, C4<0>, C4<0>;
+v0x560808833e80_0 .net "A", 0 0, L_0x560808844a40;  1 drivers
+v0x560808833f40_0 .net "B", 0 0, L_0x560808844bb0;  1 drivers
+v0x560808834010_0 .net "Carry", 0 0, L_0x560808844ce0;  1 drivers
+v0x560808834110_0 .net "CarryO", 0 0, L_0x5608088449d0;  1 drivers
+v0x5608088341b0_0 .net "Sum", 0 0, L_0x560808844960;  1 drivers
+v0x5608088342a0_0 .net "and1", 0 0, L_0x560808844780;  1 drivers
+v0x560808834370_0 .net "and2", 0 0, L_0x560808844860;  1 drivers
+v0x560808834440_0 .net "xor1", 0 0, L_0x5608088447f0;  1 drivers
+S_0x560808833220 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808832f90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808844780 .functor AND 1, L_0x560808844a40, L_0x560808844bb0, C4<1>, C4<1>;
+L_0x5608088447f0 .functor XOR 1, L_0x560808844a40, L_0x560808844bb0, C4<0>, C4<0>;
+v0x5608088334a0_0 .net "A", 0 0, L_0x560808844a40;  alias, 1 drivers
+v0x560808833560_0 .net "B", 0 0, L_0x560808844bb0;  alias, 1 drivers
+v0x560808833620_0 .net "Carry", 0 0, L_0x560808844780;  alias, 1 drivers
+v0x5608088336f0_0 .net "Sum", 0 0, L_0x5608088447f0;  alias, 1 drivers
+S_0x560808833860 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808832f90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808844860 .functor AND 1, L_0x5608088447f0, L_0x560808844ce0, C4<1>, C4<1>;
+L_0x560808844960 .functor XOR 1, L_0x5608088447f0, L_0x560808844ce0, C4<0>, C4<0>;
+v0x560808833ad0_0 .net "A", 0 0, L_0x5608088447f0;  alias, 1 drivers
+v0x560808833ba0_0 .net "B", 0 0, L_0x560808844ce0;  alias, 1 drivers
+v0x560808833c40_0 .net "Carry", 0 0, L_0x560808844860;  alias, 1 drivers
+v0x560808833d10_0 .net "Sum", 0 0, L_0x560808844960;  alias, 1 drivers
+S_0x560808834530 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608088301a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x560808845330 .functor OR 1, L_0x560808844f50, L_0x560808845120, C4<0>, C4<0>;
+v0x560808835410_0 .net "A", 0 0, L_0x5608088453f0;  1 drivers
+v0x5608088354d0_0 .net "B", 0 0, L_0x560808845580;  1 drivers
+v0x5608088355a0_0 .net "Carry", 0 0, L_0x560808845740;  1 drivers
+v0x5608088356a0_0 .net "CarryO", 0 0, L_0x560808845330;  alias, 1 drivers
+v0x560808835740_0 .net "Sum", 0 0, L_0x560808845270;  1 drivers
+v0x560808835830_0 .net "and1", 0 0, L_0x560808844f50;  1 drivers
+v0x560808835900_0 .net "and2", 0 0, L_0x560808845120;  1 drivers
+v0x5608088359d0_0 .net "xor1", 0 0, L_0x5608088450b0;  1 drivers
+S_0x560808834790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808834530;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808844f50 .functor AND 1, L_0x5608088453f0, L_0x560808845580, C4<1>, C4<1>;
+L_0x5608088450b0 .functor XOR 1, L_0x5608088453f0, L_0x560808845580, C4<0>, C4<0>;
+v0x560808834a10_0 .net "A", 0 0, L_0x5608088453f0;  alias, 1 drivers
+v0x560808834af0_0 .net "B", 0 0, L_0x560808845580;  alias, 1 drivers
+v0x560808834bb0_0 .net "Carry", 0 0, L_0x560808844f50;  alias, 1 drivers
+v0x560808834c80_0 .net "Sum", 0 0, L_0x5608088450b0;  alias, 1 drivers
+S_0x560808834df0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808834530;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x560808845120 .functor AND 1, L_0x5608088450b0, L_0x560808845740, C4<1>, C4<1>;
+L_0x560808845270 .functor XOR 1, L_0x5608088450b0, L_0x560808845740, C4<0>, C4<0>;
+v0x560808835060_0 .net "A", 0 0, L_0x5608088450b0;  alias, 1 drivers
+v0x560808835130_0 .net "B", 0 0, L_0x560808845740;  alias, 1 drivers
+v0x5608088351d0_0 .net "Carry", 0 0, L_0x560808845120;  alias, 1 drivers
+v0x5608088352a0_0 .net "Sum", 0 0, L_0x560808845270;  alias, 1 drivers
+    .scope S_0x560808805dd0;
+T_0 ;
+    %vpi_call 2 13 "$dumpfile", "mult.vcd" {0 0 0};
+    %vpi_call 2 14 "$dumpvars" {0 0 0};
+    %pushi/vec4 8, 0, 4;
+    %store/vec4 v0x56080883b1b0_0, 0, 4;
+    %pushi/vec4 8, 0, 4;
+    %store/vec4 v0x56080883b2a0_0, 0, 4;
+    %delay 5, 0;
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 7;
+    "N/A";
+    "<interactive>";
+    "multTB.v";
+    "multiplier.v";
+    "addition.v";
+    "fulladder.v";
+    "halfadder.v";
--- a/verilog/ALUTangTest/mult.vcd
+++ b/verilog/ALUTangTest/mult.vcd
@ -0,0 +1,449 @@
+$date
+	Sun Jan 19 14:35:11 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module multTB $end
+$var wire 8 ! Y [7:0] $end
+$var reg 4 " A [3:0] $end
+$var reg 4 # B [3:0] $end
+$scope module uut $end
+$var wire 4 $ A [3:0] $end
+$var wire 4 % B [3:0] $end
+$var wire 1 & overflow2 $end
+$var wire 1 ' overflow1 $end
+$var wire 1 ( overflow0 $end
+$var wire 4 ) b0 [3:0] $end
+$var wire 4 * a2 [3:0] $end
+$var wire 4 + a1 [3:0] $end
+$var wire 4 , a0 [3:0] $end
+$var wire 8 - Y [7:0] $end
+$var wire 5 . S2 [4:0] $end
+$var wire 5 / S1 [4:0] $end
+$var wire 5 0 S0 [4:0] $end
+$scope module add0 $end
+$var wire 4 1 A [3:0] $end
+$var wire 4 2 B [3:0] $end
+$var wire 1 3 CarryIN $end
+$var wire 1 ( overflow $end
+$var wire 4 4 Y [3:0] $end
+$var wire 1 5 CarryOUT $end
+$var wire 3 6 Carry4 [2:0] $end
+$scope module f0 $end
+$var wire 1 7 A $end
+$var wire 1 8 B $end
+$var wire 1 3 Carry $end
+$var wire 1 9 CarryO $end
+$var wire 1 : xor1 $end
+$var wire 1 ; and2 $end
+$var wire 1 < and1 $end
+$var wire 1 = Sum $end
+$scope module h1 $end
+$var wire 1 7 A $end
+$var wire 1 8 B $end
+$var wire 1 < Carry $end
+$var wire 1 : Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 : A $end
+$var wire 1 3 B $end
+$var wire 1 ; Carry $end
+$var wire 1 = Sum $end
+$upscope $end
+$upscope $end
+$scope module f1 $end
+$var wire 1 > A $end
+$var wire 1 ? B $end
+$var wire 1 @ Carry $end
+$var wire 1 A CarryO $end
+$var wire 1 B xor1 $end
+$var wire 1 C and2 $end
+$var wire 1 D and1 $end
+$var wire 1 E Sum $end
+$scope module h1 $end
+$var wire 1 > A $end
+$var wire 1 ? B $end
+$var wire 1 D Carry $end
+$var wire 1 B Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 B A $end
+$var wire 1 @ B $end
+$var wire 1 C Carry $end
+$var wire 1 E Sum $end
+$upscope $end
+$upscope $end
+$scope module f2 $end
+$var wire 1 F A $end
+$var wire 1 G B $end
+$var wire 1 H Carry $end
+$var wire 1 I CarryO $end
+$var wire 1 J xor1 $end
+$var wire 1 K and2 $end
+$var wire 1 L and1 $end
+$var wire 1 M Sum $end
+$scope module h1 $end
+$var wire 1 F A $end
+$var wire 1 G B $end
+$var wire 1 L Carry $end
+$var wire 1 J Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 J A $end
+$var wire 1 H B $end
+$var wire 1 K Carry $end
+$var wire 1 M Sum $end
+$upscope $end
+$upscope $end
+$scope module f3 $end
+$var wire 1 N A $end
+$var wire 1 O B $end
+$var wire 1 P Carry $end
+$var wire 1 5 CarryO $end
+$var wire 1 Q xor1 $end
+$var wire 1 R and2 $end
+$var wire 1 S and1 $end
+$var wire 1 T Sum $end
+$scope module h1 $end
+$var wire 1 N A $end
+$var wire 1 O B $end
+$var wire 1 S Carry $end
+$var wire 1 Q Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 Q A $end
+$var wire 1 P B $end
+$var wire 1 R Carry $end
+$var wire 1 T Sum $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module add1 $end
+$var wire 4 U A [3:0] $end
+$var wire 4 V B [3:0] $end
+$var wire 1 W CarryIN $end
+$var wire 1 ' overflow $end
+$var wire 4 X Y [3:0] $end
+$var wire 1 Y CarryOUT $end
+$var wire 3 Z Carry4 [2:0] $end
+$scope module f0 $end
+$var wire 1 [ A $end
+$var wire 1 \ B $end
+$var wire 1 W Carry $end
+$var wire 1 ] CarryO $end
+$var wire 1 ^ xor1 $end
+$var wire 1 _ and2 $end
+$var wire 1 ` and1 $end
+$var wire 1 a Sum $end
+$scope module h1 $end
+$var wire 1 [ A $end
+$var wire 1 \ B $end
+$var wire 1 ` Carry $end
+$var wire 1 ^ Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 ^ A $end
+$var wire 1 W B $end
+$var wire 1 _ Carry $end
+$var wire 1 a Sum $end
+$upscope $end
+$upscope $end
+$scope module f1 $end
+$var wire 1 b A $end
+$var wire 1 c B $end
+$var wire 1 d Carry $end
+$var wire 1 e CarryO $end
+$var wire 1 f xor1 $end
+$var wire 1 g and2 $end
+$var wire 1 h and1 $end
+$var wire 1 i Sum $end
+$scope module h1 $end
+$var wire 1 b A $end
+$var wire 1 c B $end
+$var wire 1 h Carry $end
+$var wire 1 f Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 f A $end
+$var wire 1 d B $end
+$var wire 1 g Carry $end
+$var wire 1 i Sum $end
+$upscope $end
+$upscope $end
+$scope module f2 $end
+$var wire 1 j A $end
+$var wire 1 k B $end
+$var wire 1 l Carry $end
+$var wire 1 m CarryO $end
+$var wire 1 n xor1 $end
+$var wire 1 o and2 $end
+$var wire 1 p and1 $end
+$var wire 1 q Sum $end
+$scope module h1 $end
+$var wire 1 j A $end
+$var wire 1 k B $end
+$var wire 1 p Carry $end
+$var wire 1 n Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 n A $end
+$var wire 1 l B $end
+$var wire 1 o Carry $end
+$var wire 1 q Sum $end
+$upscope $end
+$upscope $end
+$scope module f3 $end
+$var wire 1 r A $end
+$var wire 1 s B $end
+$var wire 1 t Carry $end
+$var wire 1 Y CarryO $end
+$var wire 1 u xor1 $end
+$var wire 1 v and2 $end
+$var wire 1 w and1 $end
+$var wire 1 x Sum $end
+$scope module h1 $end
+$var wire 1 r A $end
+$var wire 1 s B $end
+$var wire 1 w Carry $end
+$var wire 1 u Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 u A $end
+$var wire 1 t B $end
+$var wire 1 v Carry $end
+$var wire 1 x Sum $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module add2 $end
+$var wire 4 y A [3:0] $end
+$var wire 4 z B [3:0] $end
+$var wire 1 { CarryIN $end
+$var wire 1 & overflow $end
+$var wire 4 | Y [3:0] $end
+$var wire 1 } CarryOUT $end
+$var wire 3 ~ Carry4 [2:0] $end
+$scope module f0 $end
+$var wire 1 !" A $end
+$var wire 1 "" B $end
+$var wire 1 { Carry $end
+$var wire 1 #" CarryO $end
+$var wire 1 $" xor1 $end
+$var wire 1 %" and2 $end
+$var wire 1 &" and1 $end
+$var wire 1 '" Sum $end
+$scope module h1 $end
+$var wire 1 !" A $end
+$var wire 1 "" B $end
+$var wire 1 &" Carry $end
+$var wire 1 $" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 $" A $end
+$var wire 1 { B $end
+$var wire 1 %" Carry $end
+$var wire 1 '" Sum $end
+$upscope $end
+$upscope $end
+$scope module f1 $end
+$var wire 1 (" A $end
+$var wire 1 )" B $end
+$var wire 1 *" Carry $end
+$var wire 1 +" CarryO $end
+$var wire 1 ," xor1 $end
+$var wire 1 -" and2 $end
+$var wire 1 ." and1 $end
+$var wire 1 /" Sum $end
+$scope module h1 $end
+$var wire 1 (" A $end
+$var wire 1 )" B $end
+$var wire 1 ." Carry $end
+$var wire 1 ," Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 ," A $end
+$var wire 1 *" B $end
+$var wire 1 -" Carry $end
+$var wire 1 /" Sum $end
+$upscope $end
+$upscope $end
+$scope module f2 $end
+$var wire 1 0" A $end
+$var wire 1 1" B $end
+$var wire 1 2" Carry $end
+$var wire 1 3" CarryO $end
+$var wire 1 4" xor1 $end
+$var wire 1 5" and2 $end
+$var wire 1 6" and1 $end
+$var wire 1 7" Sum $end
+$scope module h1 $end
+$var wire 1 0" A $end
+$var wire 1 1" B $end
+$var wire 1 6" Carry $end
+$var wire 1 4" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 4" A $end
+$var wire 1 2" B $end
+$var wire 1 5" Carry $end
+$var wire 1 7" Sum $end
+$upscope $end
+$upscope $end
+$scope module f3 $end
+$var wire 1 8" A $end
+$var wire 1 9" B $end
+$var wire 1 :" Carry $end
+$var wire 1 } CarryO $end
+$var wire 1 ;" xor1 $end
+$var wire 1 <" and2 $end
+$var wire 1 =" and1 $end
+$var wire 1 >" Sum $end
+$scope module h1 $end
+$var wire 1 8" A $end
+$var wire 1 9" B $end
+$var wire 1 =" Carry $end
+$var wire 1 ;" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 ;" A $end
+$var wire 1 :" B $end
+$var wire 1 <" Carry $end
+$var wire 1 >" Sum $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+1>"
+0="
+0<"
+1;"
+0:"
+09"
+18"
+07"
+06"
+05"
+04"
+03"
+02"
+01"
+00"
+0/"
+0."
+0-"
+0,"
+0+"
+0*"
+0)"
+0("
+0'"
+0&"
+0%"
+0$"
+0#"
+0""
+0!"
+b0 ~
+0}
+b1000 |
+0{
+b0 z
+b1000 y
+0x
+0w
+0v
+0u
+0t
+0s
+0r
+0q
+0p
+0o
+0n
+0m
+0l
+0k
+0j
+0i
+0h
+0g
+0f
+0e
+0d
+0c
+0b
+0a
+0`
+0_
+0^
+0]
+0\
+0[
+b0 Z
+0Y
+b0 X
+0W
+b0 V
+b0 U
+0T
+0S
+0R
+0Q
+0P
+0O
+0N
+0M
+0L
+0K
+0J
+0I
+0H
+0G
+0F
+0E
+0D
+0C
+0B
+0A
+0@
+0?
+0>
+0=
+0<
+0;
+0:
+09
+08
+07
+b0 6
+05
+b0 4
+03
+b0 2
+b0 1
+b0 0
+b0 /
+b1000 .
+b1000000 -
+b0 ,
+b0 +
+b1000 *
+b0 )
+0(
+0'
+0&
+b1000 %
+b1000 $
+b1000 #
+b1000 "
+b1000000 !
+$end
+#5
--- a/verilog/ALUTangTest/mult.vcdZone.Identifier
+++ b/verilog/ALUTangTest/mult.vcdZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/multTB.v
+++ b/verilog/ALUTangTest/multTB.v
@ -0,0 +1,18 @@
+module multTB();
+
+reg [3:0] A, B;
+wire [7:0] Y;
+
+multiplier uut (
+    .A(A),
+    .B(B),
+    .Y(Y)
+);
+
+initial begin
+    $dumpfile("mult.vcd");
+    $dumpvars;
+    A = 4'b1000; B = 4'b1000; #5;
+end
+
+endmodule
--- a/verilog/ALUTangTest/multTB.vZone.Identifier
+++ b/verilog/ALUTangTest/multTB.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/multiplier.v
+++ b/verilog/ALUTangTest/multiplier.v
@ -0,0 +1,76 @@
+module multiplier (
+    input [3:0] A, B,
+    output [7:0] Y
+);
+
+wire [3:0] b0, a0, a1, a2;
+wire [4:0] S0, S1, S2;
+wire carry0, carry1, carry2;
+wire overflow0, overflow1, overflow2;
+
+// Partial product generation
+and (Y[0], A[0], B[0]); // LSB of the result
+
+// Generate partial products for B[0] and B[1]
+and ab00 (b0[0], A[1], B[0]);
+and ab01 (b0[1], A[2], B[0]);
+and ab02 (b0[2], A[3], B[0]);
+not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
+
+and aa00 (a0[0], A[0], B[1]);
+and aa01 (a0[1], A[1], B[1]);
+and aa02 (a0[2], A[2], B[1]);
+and aa03 (a0[3], A[3], B[1]);
+
+// First addition
+addition add0 (
+    .A(a0),
+    .B(b0),
+    .CarryIN(1'b0),
+    .Y(S0[3:0]),
+    .CarryOUT(S0[4]),
+    .overflow(overflow0)
+);
+
+// Generate partial products for B[2]
+and aa10 (a1[0], A[0], B[2]);
+and aa11 (a1[1], A[1], B[2]);
+and aa12 (a1[2], A[2], B[2]);
+and aa13 (a1[3], A[3], B[2]);
+
+// Second addition
+addition add1 (
+    .A(a1),
+    .B(S0[4:1]),
+    .CarryIN(1'b0),
+    .Y(S1[3:0]),
+    .CarryOUT(S1[4]),
+    .overflow(overflow1)
+);
+
+// Generate partial products for B[3]
+and aa20 (a2[0], A[0], B[3]);
+and aa21 (a2[1], A[1], B[3]);
+and aa22 (a2[2], A[2], B[3]);
+and aa23 (a2[3], A[3], B[3]);
+
+// Third addition
+addition add2 (
+    .A(a2),
+    .B(S1[4:1]),
+    .CarryIN(1'b0),
+    .Y(S2[3:0]),
+    .CarryOUT(S2[4]),
+    .overflow(overflow2)
+);
+
+// Combine results into the final output Y
+or o01 (Y[1], S0[0], 1'b0);
+or o02 (Y[2], S1[0], 1'b0);
+or o03 (Y[3], S2[0], 1'b0);
+or o04 (Y[4], S2[1], 1'b0);
+or o05 (Y[5], S2[2], 1'b0);
+or o06 (Y[6], S2[3], 1'b0);
+or o07 (Y[7], S2[4], 1'b0);
+
+endmodule
--- a/verilog/ALUTangTest/multiplier.vZone.Identifier
+++ b/verilog/ALUTangTest/multiplier.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/multZone.Identifier
+++ b/verilog/ALUTangTest/multZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/opCode.v
+++ b/verilog/ALUTangTest/opCode.v
@ -0,0 +1,25 @@
+module opCode (
+    input [2:0] A,
+    output [7:0] opCode
+);
+    wire and1, and2, and3, and4, notA, notB, notC;
+
+    not n1(notA, A[2]);
+    not n2(notB, A[1]);
+    not n3(notC, A[0]);
+
+    and a01(and1, A[2], A[1]);
+    and a02(and2, notA, A[1]);
+    and a03(and3, A[2], notB);
+    and a04(and4, notA, notB);
+
+    and a1(opCode[0], and4, notC);
+    and a2(opCode[1], and4, A[0]);
+    and a3(opCode[2], and2, notC);
+    and a4(opCode[3], and2, A[0]);
+    and a5(opCode[4], and3, notC);
+    and a6(opCode[5], and3, A[0]);
+    and a7(opCode[6], and1, notC);
+    and a8(opCode[7], and1, A[0]);
+
+endmodule
--- a/verilog/ALUTangTest/opCode.vZone.Identifier
+++ b/verilog/ALUTangTest/opCode.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/selector.v
+++ b/verilog/ALUTangTest/selector.v
@ -0,0 +1,20 @@
+module selector (
+    input [3:0] A,
+    input [3:0] B,
+    input [2:0] opCodeA,
+    input [1:0] select,
+    input [11:0] ALUY,
+    output reg [11:0] Y
+);
+
+always @(*) begin
+    case (select)
+        2'b00: Y = {8'b00000000, A};          // Zero-extend A to 8 bits
+        2'b01: Y = {8'b00000000, B};          // Zero-extend B to 8 bits
+        2'b10: Y = {9'b000000000, opCodeA};   // Zero-extend opCodeA to 8 bits
+        2'b11: Y = ALUY;                  // Directly assign ALUY
+        default: Y = ALUY;         // Default case for safety
+    endcase
+end
+
+endmodule
--- a/verilog/ALUTangTest/selector.vZone.Identifier
+++ b/verilog/ALUTangTest/selector.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/subtraction.v
+++ b/verilog/ALUTangTest/subtraction.v
@ -0,0 +1,16 @@
+module subtraction (
+    input [3:0] A, B,
+    input BorrowIN,
+    output [3:0] Y,
+    output BorrowOUT //Overflow signal'ini yani negatif gonderecek
+);
+
+wire [3:0] tempB;
+
+// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
+fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
+fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
+fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
+fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
+
+endmodule
--- a/verilog/ALUTangTest/subtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/subtraction.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/top
+++ b/verilog/ALUTangTest/top
--- a/verilog/ALUTangTest/top.v
+++ b/verilog/ALUTangTest/top.v
@ -0,0 +1,20 @@
+module top (
+    input [3:0] A, B,
+    input [2:0] opCodeA,
+    input [1:0] select,
+    output [1:0] led,
+    output [11:0] Y
+);
+
+wire wire1, wire2;
+wire [11:0] selectY;
+ALU a1( .A(A),
+        .B(B),
+        .opCodeA(opCodeA),
+        .CarryIN(1'b0),
+        .bcd(selectY),
+        .CarryOUT(led[0]),
+        .overflow(led[1]));
+selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
+
+endmodule
--- a/verilog/ALUTangTest/top.vcd
+++ b/verilog/ALUTangTest/top.vcd
--- a/verilog/ALUTangTest/top.vcdZone.Identifier
+++ b/verilog/ALUTangTest/top.vcdZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/top.vZone.Identifier
+++ b/verilog/ALUTangTest/top.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/topTB.v
+++ b/verilog/ALUTangTest/topTB.v
@ -0,0 +1,28 @@
+module topTB();
+
+reg [3:0] A,B;
+reg [2:0] opCodeA;
+reg [1:0] select;
+wire [1:0] led;
+wire [11:0] Y;
+
+top uut (
+    .A(A),
+    .B(B),
+    .opCodeA(opCodeA),
+    .select(select),
+    .led(led),
+    .Y(Y)
+);
+
+initial begin
+    $dumpfile("top.vcd");
+    $dumpvars;
+    A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5;
+    A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5;
+    A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b01; #5;
+    A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b11; #5;
+    $finish;
+end
+
+endmodule
--- a/verilog/ALUTangTest/topTB.vZone.Identifier
+++ b/verilog/ALUTangTest/topTB.vZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/topZone.Identifier
+++ b/verilog/ALUTangTest/topZone.Identifier
@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3