initial commit

verilog/ALU0.2/subtraction.vcd

@@ -0,0 +1,274 @@
+$date
+	Wed Dec 25 00:48:05 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module subtractionTB $end
+$var wire 4 ! Y [3:0] $end
+$var wire 1 " BorrowOUT $end
+$var reg 4 # A [3:0] $end
+$var reg 4 $ B [3:0] $end
+$var reg 1 % BorrowIN $end
+$scope module uut $end
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+$var wire 4 ' B [3:0] $end
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+$scope module f0 $end
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+$var wire 1 + B $end
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+$var wire 1 - tempD $end
+$var wire 1 . tempB2 $end
+$var wire 1 / tempB1 $end
+$var wire 1 0 Difference $end
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+$upscope $end
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+$var wire 1 8 tempB2 $end
+$var wire 1 9 tempB1 $end
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+$var wire 1 > B $end
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+$var wire 1 @ BorrowOut $end
+$var wire 1 A tempD $end
+$var wire 1 B tempB2 $end
+$var wire 1 C tempB1 $end
+$var wire 1 D Difference $end
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+$var wire 1 H B $end
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+$var wire 1 " BorrowOut $end
+$var wire 1 J tempD $end
+$var wire 1 K tempB2 $end
+$var wire 1 L tempB1 $end
+$var wire 1 M Difference $end
+$scope module hf1 $end
+$var wire 1 G A $end
+$var wire 1 H B $end
+$var wire 1 L Borrow $end
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+$upscope $end
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+$var wire 1 I B $end
+$var wire 1 K Borrow $end
+$var wire 1 M Difference $end
+$var wire 1 O notA $end
+$upscope $end
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+$upscope $end
+$enddefinitions $end
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