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k0rrluna
2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
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verilog/ALU0.2/opCodeTB.v Normal file
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module opCodeTB();
reg [2:0] A;
wire [7:0] opCode;
opCode uut (
.A(A),
.opCode(opCode)
);
initial begin
$dumpfile("opCode.vcd");
$dumpvars;
A = 3'b000; #3;
A = 3'b001; #3;
A = 3'b010; #3;
A = 3'b011; #3;
A = 3'b100; #3;
A = 3'b101; #3;
A = 3'b110; #3;
A = 3'b111; #3;
$finish;
end
endmodule