initial commit

2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
--- a/verilog/ALU0.2/multiplierTB.v
+++ b/verilog/ALU0.2/multiplierTB.v
@ -0,0 +1,22 @@
+module multiplierTB();
+reg [3:0] A, B;
+wire [7:0] Y;
+
+multiplier uut(
+    .A(A),
+    .B(B),
+    .Y(Y)
+);
+
+initial begin
+    $dumpfile("multiplier.vcd");
+    $dumpvars;
+    A = 4'b0000; B = 4'b0000; #2;
+    A = 4'b0000; B = 4'b1000; #2;
+    A = 4'b1000; B = 4'b1000; #2;
+    A = 4'b0111; B = 4'b0111; #2;
+    A = 4'b1111; B = 4'b1111; #2;
+    $finish;
+end
+
+endmodule