initial commit

2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
--- a/verilog/ALU0.2/!NOTUSE!overflowDetect.v
+++ b/verilog/ALU0.2/!NOTUSE!overflowDetect.v
@@ -0,0 +1,29 @@
+module overflowDetect (
+    input [1:0] opCode,
+    input [3:0] A, B,
+    input [3:0] Y,
+    input CarryOUT,
+    output overflowDetect
+);
+
+wire opC;
+wire sign1, sign2, sign3, sign4;
+wire addOverflow, subOverflow;
+wire detect1, detect2;
+
+or o1 (opC, opCode[0], opCode[1]); //check add or sub
+
+xnor xno1 (sign1, A[3], B[3]); // A B same sign
+xor xo2 (sign3, A[3], B[3]); // A and B opposite sign
+
+xor xo1 (sign2, Y[3], A[3]); // A and Sum opposite sign
+
+and a01 (addOverflow, sign1, opCode[0]); // A B same for add
+and a02 (subOverflow, sign3, opCode[1]); // A B diff for sub
+
+or o2 (detect1, addOverflow, subOverflow);
+
+and a03(detect2, detect1, sign2);
+and a04(overflowDetect, opC, detect2);
+
+endmodule
--- a/verilog/ALU0.2/!NOTUSE!overflowDetect.vZone.Identifier
+++ b/verilog/ALU0.2/!NOTUSE!overflowDetect.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/!NOTUSE!selector.v
+++ b/verilog/ALU0.2/!NOTUSE!selector.v
@@ -0,0 +1,68 @@
+module selector (
+    input [3:0] select,
+    input [7:0] Y,
+    input [3:0] A, B,
+    input [2:0] opCodeA,
+    output [7:0] s0
+);
+
+wire [3:0] a0, b0, tempAB, tempYO;
+wire [7:0] y0;
+wire [2:0] op0;
+wire tempsO, temps;
+
+// Select signals for A
+and a00 (a0[0], select[0], A[0]);
+and a01 (a0[1], select[0], A[1]);
+and a02 (a0[2], select[0], A[2]);
+and a03 (a0[3], select[0], A[3]);
+
+// Select signals for B
+and b00 (b0[0], select[1], B[0]);
+and b01 (b0[1], select[1], B[1]);
+and b02 (b0[2], select[1], B[2]);
+and b03 (b0[3], select[1], B[3]);
+
+// Select signals for Y
+and y00 (y0[0], select[2], Y[0]);
+and y01 (y0[1], select[2], Y[1]);
+and y02 (y0[2], select[2], Y[2]);
+and y03 (y0[3], select[2], Y[3]);
+and y04 (y0[4], select[2], Y[4]);
+and y05 (y0[5], select[2], Y[5]);
+and y06 (y0[6], select[2], Y[6]);
+and y07 (y0[7], select[2], Y[7]);
+
+// Select signals for opCodeA
+and op00 (op0[0], select[3], opCodeA[0]);
+and op01 (op0[1], select[3], opCodeA[1]);
+and op02 (op0[2], select[3], opCodeA[2]);
+
+// Combine A and B
+or or1 (tempAB[0], a0[0], b0[0]);
+or or2 (tempAB[1], a0[1], b0[1]);
+or or3 (tempAB[2], a0[2], b0[2]);
+or or4 (tempAB[3], a0[3], b0[3]);
+
+// Combine Y and opCodeA
+or or5 (tempYO[0], y0[0], op0[0]);
+or or6 (tempYO[1], y0[1], op0[1]);
+or or7 (tempYO[2], y0[2], op0[2]);
+or or8 (tempYO[3], y0[3], 1'b0);
+
+// NOR for select logic
+nor s01 (tempsO, select[0], select[1]);
+nor s02 (temps, tempsO, select[3]);
+
+// Final s0 connections
+or or9 (s0[0], tempAB[0], tempYO[0]);
+or or10 (s0[1], tempAB[1], tempYO[1]);
+or or11 (s0[2], tempAB[2], tempYO[2]);
+or or12 (s0[3], tempAB[3], tempYO[3]);
+
+and and13 (s0[4], y0[4], temps);
+and and14 (s0[5], y0[5], temps);
+and and15 (s0[6], y0[6], temps);
+and and16 (s0[7], y0[7], temps);
+
+endmodule
--- a/verilog/ALU0.2/!NOTUSE!selector.vZone.Identifier
+++ b/verilog/ALU0.2/!NOTUSE!selector.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/ALU
+++ b/verilog/ALU0.2/ALU
--- a/verilog/ALU0.2/ALU.v
+++ b/verilog/ALU0.2/ALU.v
@@ -0,0 +1,79 @@
+module ALU (
+    input [3:0] A, B,
+    input CarryIN,
+    input [2:0] opCodeA,
+    output [7:0] Y,
+    output CarryOUT, overflow
+);
+
+// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
+
+wire [7:0] opCode8;
+wire [3:0] add_Y, sub_Y;
+wire [3:0] resultA, resultO, resultX, lUOutput1;
+wire [3:0] aUtemp1, aUtemp2, lUOutput2;
+wire [3:0] wireY, wireLA;
+wire [7:0] opwireM, wireM, Y;
+
+opCode opCd (.A(opCodeA), .opCode(opCode8));
+
+arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
+logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
+multiplier mU (.A(A), .B(B), .Y(opwireM));
+
+or o01 (lUOutput1[0], resultA[0], resultO[0]);
+or o02 (lUOutput1[1], resultA[1], resultO[1]);
+or o03 (lUOutput1[2], resultA[2], resultO[2]);
+or o04 (lUOutput1[3], resultA[3], resultO[3]);
+
+or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
+or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
+or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
+or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
+
+
+and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
+and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
+and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
+and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
+
+
+and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
+and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
+and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
+and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
+
+and a21 (wireM[0], opCode8[2], opwireM[0]);
+and a22 (wireM[1], opCode8[2], opwireM[1]);
+and a23 (wireM[2], opCode8[2], opwireM[2]);
+and a24 (wireM[3], opCode8[2], opwireM[3]);
+and a25 (wireM[4], opCode8[2], opwireM[4]);
+and a26 (wireM[5], opCode8[2], opwireM[5]);
+and a27 (wireM[6], opCode8[2], opwireM[6]);
+and a28 (wireM[7], opCode8[2], opwireM[7]);
+
+
+or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
+or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
+or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
+or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
+
+
+or o1 (wireLA[0], lUOutput2[0], wireY[0]);
+or o2 (wireLA[1], lUOutput2[1], wireY[1]);
+or o3 (wireLA[2], lUOutput2[2], wireY[2]);
+or o4 (wireLA[3], lUOutput2[3], wireY[3]);
+
+or o31 (Y[0], wireLA[0], wireM[0]);
+or o32 (Y[1], wireLA[1], wireM[1]);
+or o33 (Y[2], wireLA[2], wireM[2]);
+or o34 (Y[3], wireLA[3], wireM[3]);
+or o35 (Y[4], 1'b0, wireM[4]);
+or o36 (Y[5], 1'b0, wireM[5]);
+or o37 (Y[6], 1'b0, wireM[6]);
+or o38 (Y[7], 1'b0, wireM[7]);
+
+//BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
+
+
+endmodule
--- a/verilog/ALU0.2/ALU.vcd
+++ b/verilog/ALU0.2/ALU.vcd
--- a/verilog/ALU0.2/ALU.vcdZone.Identifier
+++ b/verilog/ALU0.2/ALU.vcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/ALU.vZone.Identifier
+++ b/verilog/ALU0.2/ALU.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/ALUTB.v
+++ b/verilog/ALU0.2/ALUTB.v
@@ -0,0 +1,42 @@
+module ALUTB ();
+
+reg [3:0] A, B;
+reg CarryIN;
+reg [2:0] opCodeA;
+wire CarryOUT, overflow;
+wire [11:0] bcd;
+
+ALU uut(
+    .A(A),
+    .B(B),
+    .CarryIN(CarryIN),
+    .opCodeA(opCodeA),
+    .CarryOUT(CarryOUT),
+    .bcd(bcd),
+    .overflow(overflow)
+);
+
+initial begin
+    $dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
+    $dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
+    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
+    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b011; #5;
+    A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
+    A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
+    A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
+
+    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
+    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b111; #5;
+    A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
+    A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
+    A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
+
+    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
+    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b010; #5;
+    A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
+    A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
+    A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
+    $finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
+end
+
+endmodule
--- a/verilog/ALU0.2/ALUTB.vZone.Identifier
+++ b/verilog/ALU0.2/ALUTB.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/ALUZone.Identifier
+++ b/verilog/ALU0.2/ALUZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/BinaryToBCD.v
+++ b/verilog/ALU0.2/BinaryToBCD.v
@@ -0,0 +1,79 @@
+module BinaryToBCD (
+    input [7:0] binary,
+    output [11:0] bcd
+);
+
+wire empty1, empty2;
+wire [3:0] dab1, dab2, dab3, dab4, dab5;
+
+and a111 (empty1, 1'b0, 1'b0);
+and a000 (empty2, 1'b0, 1'b0);
+and a222 (bcd[11], 1'b0, 1'b0);
+and a223 (bcd[10], 1'b0, 1'b0);
+
+dabble d1t (.A((empty1)),
+.B(binary[7]),
+.C(binary[6]),
+.D(binary[5]),
+.X(dab1[0]),
+.Y(dab1[1]),
+.Z(dab1[2]),
+.E(dab1[3]));
+
+dabble d2u (.A((dab1[1])),
+.B(dab1[2]),
+.C(dab1[3]),
+.D(binary[4]),
+.X(dab2[0]),
+.Y(dab2[1]),
+.Z(dab2[2]),
+.E(dab2[3]));
+
+dabble d3v (.A((dab2[1])),
+.B(dab2[2]),
+.C(dab2[3]),
+.D(binary[3]),
+.X(dab3[0]),
+.Y(dab3[1]),
+.Z(dab3[2]),
+.E(dab3[3]));
+
+dabble d4w (.A((empty2)),
+.B(dab1[0]),
+.C(dab2[0]),
+.D(dab3[0]),
+.X(bcd[9]),
+.Y(dab4[1]),
+.Z(dab4[2]),
+.E(dab4[3]));
+
+dabble d5x (.A((dab3[1])),
+.B(dab3[2]),
+.C(dab3[3]),
+.D(binary[2]),
+.X(dab5[0]),
+.Y(dab5[1]),
+.Z(dab5[2]),
+.E(dab5[3]));
+
+dabble d6y (.A((dab4[1])),
+.B(dab4[2]),
+.C(dab4[3]),
+.D(dab5[0]),
+.X(bcd[8]),
+.Y(bcd[7]),
+.Z(bcd[6]),
+.E(bcd[5]));
+
+dabble d7z (.A((dab5[1])),
+.B(dab5[2]),
+.C(dab5[3]),
+.D(binary[1]),
+.X(bcd[4]),
+.Y(bcd[3]),
+.Z(bcd[2]),
+.E(bcd[1]));
+
+or o1 (bcd[0], binary[0], 1'b0);
+
+endmodule
--- a/verilog/ALU0.2/BinaryToBCD.vcd
+++ b/verilog/ALU0.2/BinaryToBCD.vcd
@@ -0,0 +1,568 @@
+$date
+	Mon Dec 23 02:48:47 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module BinaryToBCDTB $end
+$var wire 12 ! bcd [11:0] $end
+$var reg 8 " binary [7:0] $end
+$scope module uut $end
+$var wire 8 # binary [7:0] $end
+$var wire 1 $ empty1 $end
+$var wire 1 % empty2 $end
+$var wire 4 & dab5 [3:0] $end
+$var wire 4 ' dab4 [3:0] $end
+$var wire 4 ( dab3 [3:0] $end
+$var wire 4 ) dab2 [3:0] $end
+$var wire 4 * dab1 [3:0] $end
+$var wire 12 + bcd [11:0] $end
+$scope module d1t $end
+$var wire 1 $ A $end
+$var wire 1 , B $end
+$var wire 1 - C $end
+$var wire 1 . D $end
+$var wire 1 / E $end
+$var wire 1 0 X $end
+$var wire 1 1 Y $end
+$var wire 1 2 Z $end
+$var wire 1 3 nor1 $end
+$var wire 1 4 nor2 $end
+$var wire 1 5 nor3 $end
+$var wire 1 6 or1 $end
+$var wire 1 7 xor1 $end
+$var wire 1 8 xor2 $end
+$upscope $end
+$scope module d2u $end
+$var wire 1 9 A $end
+$var wire 1 : B $end
+$var wire 1 ; C $end
+$var wire 1 < D $end
+$var wire 1 = E $end
+$var wire 1 > X $end
+$var wire 1 ? Y $end
+$var wire 1 @ Z $end
+$var wire 1 A nor1 $end
+$var wire 1 B nor2 $end
+$var wire 1 C nor3 $end
+$var wire 1 D or1 $end
+$var wire 1 E xor1 $end
+$var wire 1 F xor2 $end
+$upscope $end
+$scope module d3v $end
+$var wire 1 G A $end
+$var wire 1 H B $end
+$var wire 1 I C $end
+$var wire 1 J D $end
+$var wire 1 K E $end
+$var wire 1 L X $end
+$var wire 1 M Y $end
+$var wire 1 N Z $end
+$var wire 1 O nor1 $end
+$var wire 1 P nor2 $end
+$var wire 1 Q nor3 $end
+$var wire 1 R or1 $end
+$var wire 1 S xor1 $end
+$var wire 1 T xor2 $end
+$upscope $end
+$scope module d4w $end
+$var wire 1 % A $end
+$var wire 1 U B $end
+$var wire 1 V C $end
+$var wire 1 W D $end
+$var wire 1 X E $end
+$var wire 1 Y X $end
+$var wire 1 Z Y $end
+$var wire 1 [ Z $end
+$var wire 1 \ nor1 $end
+$var wire 1 ] nor2 $end
+$var wire 1 ^ nor3 $end
+$var wire 1 _ or1 $end
+$var wire 1 ` xor1 $end
+$var wire 1 a xor2 $end
+$upscope $end
+$scope module d5x $end
+$var wire 1 b A $end
+$var wire 1 c B $end
+$var wire 1 d C $end
+$var wire 1 e D $end
+$var wire 1 f E $end
+$var wire 1 g X $end
+$var wire 1 h Y $end
+$var wire 1 i Z $end
+$var wire 1 j nor1 $end
+$var wire 1 k nor2 $end
+$var wire 1 l nor3 $end
+$var wire 1 m or1 $end
+$var wire 1 n xor1 $end
+$var wire 1 o xor2 $end
+$upscope $end
+$scope module d6y $end
+$var wire 1 p A $end
+$var wire 1 q B $end
+$var wire 1 r C $end
+$var wire 1 s D $end
+$var wire 1 t E $end
+$var wire 1 u X $end
+$var wire 1 v Y $end
+$var wire 1 w Z $end
+$var wire 1 x nor1 $end
+$var wire 1 y nor2 $end
+$var wire 1 z nor3 $end
+$var wire 1 { or1 $end
+$var wire 1 | xor1 $end
+$var wire 1 } xor2 $end
+$upscope $end
+$scope module d7z $end
+$var wire 1 ~ A $end
+$var wire 1 !" B $end
+$var wire 1 "" C $end
+$var wire 1 #" D $end
+$var wire 1 $" E $end
+$var wire 1 %" X $end
+$var wire 1 &" Y $end
+$var wire 1 '" Z $end
+$var wire 1 (" nor1 $end
+$var wire 1 )" nor2 $end
+$var wire 1 *" nor3 $end
+$var wire 1 +" or1 $end
+$var wire 1 ," xor1 $end
+$var wire 1 -" xor2 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0-"
+0,"
+1+"
+0*"
+1)"
+1("
+0'"
+0&"
+0%"
+0$"
+0#"
+0""
+0!"
+0~
+0}
+0|
+1{
+0z
+1y
+1x
+0w
+0v
+0u
+0t
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+0o
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+1]
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+0Y
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+0T
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+1R
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+0I
+0H
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+1A
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+0?
+0>
+0=
+0<
+0;
+0:
+09
+08
+07
+16
+05
+14
+13
+02
+01
+00
+0/
+0.
+0-
+0,
+b0 +
+b0 *
+b0 )
+b0 (
+b0z '
+b0 &
+0%
+0$
+b0 #
+b0 "
+b0 !
+$end
+#10
+1%"
+1*"
+0("
+1!"
+0k
+b100 &
+1i
+1o
+0P
+1d
+0)"
+1S
+b1000 (
+1K
+1,"
+b10000 !
+b10000 +
+0$"
+1J
+1#"
+b1010 "
+b1010 #
+#20
+0%"
+1$"
+0*"
+0y
+b1000010 !
+b1000010 +
+1w
+1("
+1}
+0!"
+0]
+1r
+1k
+b0 &
+0i
+1`
+b100z '
+1X
+0o
+1W
+0d
+1L
+b1 (
+0K
+1Q
+0O
+1H
+0B
+b100 )
+1@
+1F
+04
+1;
+17
+b1000 *
+1/
+1.
+b101010 "
+b101010 #
+#30
+1&"
+0+"
+1v
+0,"
+1y
+0{
+1~
+0u
+1h
+0z
+0m
+0x
+1q
+1c
+0'"
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+1N
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+1T
+1O
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+0s
+0""
+1%"
+0$"
+1V
+1I
+0H
+0]
+0r
+0g
+0f
+1*"
+1>
+1=
+b1001 )
+0@
+0`
+b10z '
+0X
+0l
+0("
+1C
+0D
+0W
+0n
+0j
+0!"
+0A
+0L
+0b
+1k
+b10 &
+0i
+1:
+0Q
+0M
+0o
+b1100 *
+12
+0P
+1R
+0d
+18
+0S
+b100 (
+0K
+b10011001 !
+b10011001 +
+1-
+0J
+b1100011 "
+b1100011 #
+#40
+1w
+1n
+1b
+1M
+1}
+1u
+0R
+1r
+1z
+0v
+1`
+b110z '
+1X
+1!"
+0y
+1{
+1G
+1W
+1i
+1|
+0t
+1?
+1L
+1m
+1s
+1""
+1%"
+1Q
+0j
+1g
+1f
+1*"
+0)"
+0O
+0c
+1l
+0("
+1-"
+19
+0H
+0N
+0k
+0~
+0:
+11
+1F
+0@
+1T
+1o
+b1101 &
+0h
+0&"
+0'"
+02
+14
+06
+0;
+0D
+0I
+0d
+0+"
+03
+08
+07
+b10 *
+0/
+0E
+b11 )
+0=
+0S
+b11 (
+0K
+0,"
+b101010011 !
+b101010011 +
+1$"
+1,
+0-
+0.
+1<
+1J
+0#"
+b10011001 "
+b10011001 #
+#50
+0t
+1{
+1w
+0y
+1}
+1%"
+0|
+0u
+1r
+1*"
+0s
+0z
+1X
+1o
+0("
+0g
+1x
+0_
+0l
+0q
+0c
+0`
+1j
+b100z '
+0[
+0N
+1Y
+0W
+1d
+0b
+1a
+1^
+0L
+1K
+b1000 (
+0M
+0&"
+1V
+0I
+0H
+0\
+0F
+0Q
+1R
+1>
+0=
+0@
+1U
+1S
+1O
+0T
+1C
+1D
+10
+0G
+0~
+1!"
+1:
+1E
+0A
+15
+b1 )
+0?
+0h
+1i
+1-"
+1'"
+12
+09
+04
+16
+0;
+1m
+1""
+1+"
+18
+01
+17
+b101 *
+0/
+1n
+b1100 &
+1f
+1,"
+b1001010101 !
+b1001010101 +
+0$"
+1-
+1.
+1e
+1#"
+b11111111 "
+b11111111 #
+#60
--- a/verilog/ALU0.2/BinaryToBCD.vcdZone.Identifier
+++ b/verilog/ALU0.2/BinaryToBCD.vcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/BinaryToBCD.vZone.Identifier
+++ b/verilog/ALU0.2/BinaryToBCD.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/BinaryToBCDTB.v
+++ b/verilog/ALU0.2/BinaryToBCDTB.v
@@ -0,0 +1,40 @@
+module BinaryToBCDTB;
+    // Testbench signals
+    reg [7:0] binary;
+    wire [11:0] bcd; // Output BCD
+
+    // Instantiate the BinaryToBCD module
+    BinaryToBCD uut (
+        .binary(binary),
+        .bcd(bcd)
+    );
+
+    // Testbench procedure
+    initial begin
+        $monitor("Time: %0t | Binary: %b | BCD: %b (Hundreds: %d, Tens: %d, Ones: %d)",
+                 $time, binary, bcd, bcd[11:8], bcd[7:4], bcd[3:0]);
+        $dumpfile("BinaryToBCD.vcd");
+        $dumpvars;
+        // Test cases
+        binary = 8'b00000000; // Decimal: 0
+        #10;
+
+        binary = 8'b00001010; // Decimal: 10
+        #10;
+
+        binary = 8'b00101010; // Decimal: 42
+        #10;
+
+        binary = 8'b01100011; // Decimal: 99
+        #10;
+
+        binary = 8'b10011001; // Decimal: 153
+        #10;
+
+        binary = 8'b11111111; // Decimal: 255
+        #10;
+
+        // End simulation
+        $finish;
+    end
+endmodule
--- a/verilog/ALU0.2/BinaryToBCDTB.vZone.Identifier
+++ b/verilog/ALU0.2/BinaryToBCDTB.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/addition.v
+++ b/verilog/ALU0.2/addition.v
@@ -0,0 +1,20 @@
+module addition (
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [2:0] Carry4;
+
+fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
+fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
+fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
+fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
+
+
+//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
+xor ov1 (overflow, Carry4[2], CarryOUT);
+
+endmodule
--- a/verilog/ALU0.2/addition.vZone.Identifier
+++ b/verilog/ALU0.2/addition.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/arithmeticUnit.v
+++ b/verilog/ALU0.2/arithmeticUnit.v
@@ -0,0 +1,33 @@
+module arithmeticUnit (
+    input [1:0] opCode,
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] add_Y, sub_Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [3:0] addY, subY;
+wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
+
+addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
+subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
+
+and add1 (add_Y[0], opCode[0], addY[0]);
+and add2 (add_Y[1], opCode[0], addY[1]);
+and add3 (add_Y[2], opCode[0], addY[2]);
+and add4 (add_Y[3], opCode[0], addY[3]);
+
+and sub1 (sub_Y[0], opCode[1], subY[0]);
+and sub2 (sub_Y[1], opCode[1], subY[1]);
+and sub3 (sub_Y[2], opCode[1], subY[2]);
+and sub4 (sub_Y[3], opCode[1], subY[3]);
+
+// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
+and and10 (tempCSub, CarryOUTSUB, opCode[1]);
+and and11 (tempCAdd, CarryOUTADD, opCode[0]);
+or or4 (CarryOUT, tempCAdd, tempCSub);
+
+and add12 (overflow, opCode[0], tempoverflow);
+
+endmodule
--- a/verilog/ALU0.2/arithmeticUnit.vZone.Identifier
+++ b/verilog/ALU0.2/arithmeticUnit.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/binarytobcd
+++ b/verilog/ALU0.2/binarytobcd
@@ -0,0 +1,362 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x56140140d330 .scope module, "BinaryToBCDTB" "BinaryToBCDTB" 2 1;
+ .timescale 0 0;
+v0x561401436a70_0 .net "bcd", 11 0, L_0x56140143cdd0;  1 drivers
+v0x561401436b30_0 .var "binary", 7 0;
+S_0x56140140a900 .scope module, "uut" "BinaryToBCD" 2 7, 3 1 0, S_0x56140140d330;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "binary";
+    .port_info 1 /OUTPUT 12 "bcd";
+L_0x7f952d86e018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x7f952d86e060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x561401413c60 .functor AND 1, L_0x7f952d86e018, L_0x7f952d86e060, C4<1>, C4<1>;
+L_0x7f952d86e0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x7f952d86e0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x561401436c90 .functor AND 1, L_0x7f952d86e0a8, L_0x7f952d86e0f0, C4<1>, C4<1>;
+L_0x7f952d86e138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x7f952d86e180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x561401436df0 .functor AND 1, L_0x7f952d86e138, L_0x7f952d86e180, C4<1>, C4<1>;
+L_0x7f952d86e1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x7f952d86e210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x561401436f80 .functor AND 1, L_0x7f952d86e1c8, L_0x7f952d86e210, C4<1>, C4<1>;
+L_0x7f952d86e258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x56140143d200 .functor OR 1, L_0x56140143d2c0, L_0x7f952d86e258, C4<0>, C4<0>;
+v0x561401435620_0 .net/2u *"_ivl_0", 0 0, L_0x7f952d86e018;  1 drivers
+v0x561401435720_0 .net/2u *"_ivl_10", 0 0, L_0x7f952d86e138;  1 drivers
+v0x561401435800_0 .net/2u *"_ivl_12", 0 0, L_0x7f952d86e180;  1 drivers
+v0x5614014358c0_0 .net *"_ivl_132", 0 0, L_0x56140143d200;  1 drivers
+v0x5614014359a0_0 .net *"_ivl_136", 0 0, L_0x56140143d2c0;  1 drivers
+v0x561401435a80_0 .net/2u *"_ivl_137", 0 0, L_0x7f952d86e258;  1 drivers
+v0x561401435b60_0 .net *"_ivl_14", 0 0, L_0x561401436f80;  1 drivers
+o0x7f952d8b8e48 .functor BUFZ 1, C4<z>; HiZ drive
+; Elide local net with no drivers, v0x561401435c40_0 name=_ivl_141
+v0x561401435d20_0 .net/2u *"_ivl_16", 0 0, L_0x7f952d86e1c8;  1 drivers
+v0x561401435e90_0 .net/2u *"_ivl_18", 0 0, L_0x7f952d86e210;  1 drivers
+v0x561401435f70_0 .net/2u *"_ivl_2", 0 0, L_0x7f952d86e060;  1 drivers
+v0x561401436050_0 .net/2u *"_ivl_4", 0 0, L_0x7f952d86e0a8;  1 drivers
+v0x561401436130_0 .net/2u *"_ivl_6", 0 0, L_0x7f952d86e0f0;  1 drivers
+v0x561401436210_0 .net *"_ivl_8", 0 0, L_0x561401436df0;  1 drivers
+v0x5614014362f0_0 .net "bcd", 11 0, L_0x56140143cdd0;  alias, 1 drivers
+v0x5614014363d0_0 .net "binary", 7 0, v0x561401436b30_0;  1 drivers
+v0x5614014364b0_0 .net "dab1", 3 0, L_0x561401437c20;  1 drivers
+v0x561401436590_0 .net "dab2", 3 0, L_0x561401438a60;  1 drivers
+v0x561401436670_0 .net "dab3", 3 0, L_0x561401439840;  1 drivers
+v0x561401436750_0 .net "dab4", 3 0, L_0x56140143d510;  1 drivers
+v0x561401436830_0 .net "dab5", 3 0, L_0x56140143b080;  1 drivers
+v0x561401436910_0 .net "empty1", 0 0, L_0x561401413c60;  1 drivers
+v0x5614014369b0_0 .net "empty2", 0 0, L_0x561401436c90;  1 drivers
+L_0x561401437960 .part v0x561401436b30_0, 7, 1;
+L_0x561401437a50 .part v0x561401436b30_0, 6, 1;
+L_0x561401437af0 .part v0x561401436b30_0, 5, 1;
+L_0x561401437c20 .concat8 [ 1 1 1 1], L_0x561401437500, L_0x561401437670, L_0x5614014377d0, L_0x561401437840;
+L_0x561401438630 .part L_0x561401437c20, 1, 1;
+L_0x561401438760 .part L_0x561401437c20, 2, 1;
+L_0x561401438840 .part L_0x561401437c20, 3, 1;
+L_0x561401438970 .part v0x561401436b30_0, 4, 1;
+L_0x561401438a60 .concat8 [ 1 1 1 1], L_0x5614014381d0, L_0x561401438340, L_0x5614014384a0, L_0x561401438510;
+L_0x5614014393d0 .part L_0x561401438a60, 1, 1;
+L_0x561401439560 .part L_0x561401438a60, 2, 1;
+L_0x561401439600 .part L_0x561401438a60, 3, 1;
+L_0x5614014397a0 .part v0x561401436b30_0, 3, 1;
+L_0x561401439840 .concat8 [ 1 1 1 1], L_0x561401438fb0, L_0x5614014390e0, L_0x561401439240, L_0x5614014392b0;
+L_0x56140143a190 .part L_0x561401437c20, 0, 1;
+L_0x56140143a230 .part L_0x561401438a60, 0, 1;
+L_0x56140143a360 .part L_0x561401439840, 0, 1;
+L_0x56140143acc0 .part L_0x561401439840, 1, 1;
+L_0x56140143ae90 .part L_0x561401439840, 2, 1;
+L_0x56140143af30 .part L_0x561401439840, 3, 1;
+L_0x56140143adf0 .part v0x561401436b30_0, 2, 1;
+L_0x56140143b080 .concat8 [ 1 1 1 1], L_0x56140143a8a0, L_0x56140143a9d0, L_0x56140143ab30, L_0x56140143aba0;
+L_0x56140143bac0 .part L_0x56140143d510, 1, 1;
+L_0x56140143bbf0 .part L_0x56140143d510, 2, 1;
+L_0x56140143bd60 .part L_0x56140143d510, 3, 1;
+L_0x56140143be00 .part L_0x56140143b080, 0, 1;
+L_0x56140143c840 .part L_0x56140143b080, 1, 1;
+L_0x56140143c970 .part L_0x56140143b080, 2, 1;
+L_0x56140143cb90 .part L_0x56140143b080, 3, 1;
+L_0x56140143cc30 .part v0x561401436b30_0, 1, 1;
+LS_0x56140143cdd0_0_0 .concat8 [ 1 1 1 1], L_0x56140143d200, L_0x56140143c720, L_0x56140143c6b0, L_0x56140143c550;
+LS_0x56140143cdd0_0_4 .concat8 [ 1 1 1 1], L_0x56140143c420, L_0x56140143b9a0, L_0x56140143b930, L_0x56140143b7d0;
+LS_0x56140143cdd0_0_8 .concat8 [ 1 1 1 1], L_0x56140143b6a0, L_0x561401439d70, L_0x561401436f80, L_0x561401436df0;
+L_0x56140143cdd0 .concat8 [ 4 4 4 0], LS_0x56140143cdd0_0_0, LS_0x56140143cdd0_0_4, LS_0x56140143cdd0_0_8;
+L_0x56140143d2c0 .part v0x561401436b30_0, 0, 1;
+L_0x56140143d510 .concat [ 1 1 1 1], o0x7f952d8b8e48, L_0x561401439ea0, L_0x56140143a000, L_0x56140143a070;
+S_0x561401408560 .scope module, "d1t" "dabble" 3 14, 4 1 0, S_0x56140140a900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+L_0x5614014370c0 .functor XOR 1, L_0x561401413c60, L_0x561401437af0, C4<0>, C4<0>;
+L_0x561401437130 .functor NOR 1, L_0x561401413c60, L_0x561401437960, C4<0>, C4<0>;
+L_0x561401437200 .functor XOR 1, L_0x561401413c60, L_0x561401437a50, C4<0>, C4<0>;
+L_0x5614014372d0 .functor NOR 1, L_0x5614014370c0, L_0x561401437200, C4<0>, C4<0>;
+L_0x5614014373f0 .functor NOR 1, L_0x5614014372d0, L_0x561401437130, C4<0>, C4<0>;
+L_0x561401437500 .functor BUF 1, L_0x5614014373f0, C4<0>, C4<0>, C4<0>;
+L_0x561401437600 .functor OR 1, L_0x5614014370c0, L_0x561401437130, C4<0>, C4<0>;
+L_0x561401437670 .functor NOR 1, L_0x561401437600, L_0x561401437a50, C4<0>, C4<0>;
+L_0x5614014377d0 .functor AND 1, L_0x561401437600, L_0x561401437200, C4<1>, C4<1>;
+L_0x561401437840 .functor XOR 1, L_0x5614014373f0, L_0x561401437af0, C4<0>, C4<0>;
+v0x56140140b5f0_0 .net "A", 0 0, L_0x561401413c60;  alias, 1 drivers
+v0x56140140b2e0_0 .net "B", 0 0, L_0x561401437960;  1 drivers
+v0x56140140afa0_0 .net "C", 0 0, L_0x561401437a50;  1 drivers
+v0x561401412b80_0 .net "D", 0 0, L_0x561401437af0;  1 drivers
+v0x561401412e90_0 .net "E", 0 0, L_0x561401437840;  1 drivers
+v0x5614014131a0_0 .net "X", 0 0, L_0x561401437500;  1 drivers
+v0x561401413450_0 .net "Y", 0 0, L_0x561401437670;  1 drivers
+v0x56140142f5e0_0 .net "Z", 0 0, L_0x5614014377d0;  1 drivers
+v0x56140142f6a0_0 .net "nor1", 0 0, L_0x561401437130;  1 drivers
+v0x56140142f760_0 .net "nor2", 0 0, L_0x5614014372d0;  1 drivers
+v0x56140142f820_0 .net "nor3", 0 0, L_0x5614014373f0;  1 drivers
+v0x56140142f8e0_0 .net "or1", 0 0, L_0x561401437600;  1 drivers
+v0x56140142f9a0_0 .net "xor1", 0 0, L_0x5614014370c0;  1 drivers
+v0x56140142fa60_0 .net "xor2", 0 0, L_0x561401437200;  1 drivers
+S_0x56140142fc20 .scope module, "d2u" "dabble" 3 23, 4 1 0, S_0x56140140a900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+L_0x561401437de0 .functor XOR 1, L_0x561401438630, L_0x561401438970, C4<0>, C4<0>;
+L_0x561401437e50 .functor NOR 1, L_0x561401438630, L_0x561401438760, C4<0>, C4<0>;
+L_0x561401437f10 .functor XOR 1, L_0x561401438630, L_0x561401438840, C4<0>, C4<0>;
+L_0x561401437f80 .functor NOR 1, L_0x561401437de0, L_0x561401437f10, C4<0>, C4<0>;
+L_0x5614014380c0 .functor NOR 1, L_0x561401437f80, L_0x561401437e50, C4<0>, C4<0>;
+L_0x5614014381d0 .functor BUF 1, L_0x5614014380c0, C4<0>, C4<0>, C4<0>;
+L_0x5614014382d0 .functor OR 1, L_0x561401437de0, L_0x561401437e50, C4<0>, C4<0>;
+L_0x561401438340 .functor NOR 1, L_0x5614014382d0, L_0x561401438840, C4<0>, C4<0>;
+L_0x5614014384a0 .functor AND 1, L_0x5614014382d0, L_0x561401437f10, C4<1>, C4<1>;
+L_0x561401438510 .functor XOR 1, L_0x5614014380c0, L_0x561401438970, C4<0>, C4<0>;
+v0x56140142fef0_0 .net "A", 0 0, L_0x561401438630;  1 drivers
+v0x56140142ffb0_0 .net "B", 0 0, L_0x561401438760;  1 drivers
+v0x561401430070_0 .net "C", 0 0, L_0x561401438840;  1 drivers
+v0x561401430110_0 .net "D", 0 0, L_0x561401438970;  1 drivers
+v0x5614014301d0_0 .net "E", 0 0, L_0x561401438510;  1 drivers
+v0x5614014302e0_0 .net "X", 0 0, L_0x5614014381d0;  1 drivers
+v0x5614014303a0_0 .net "Y", 0 0, L_0x561401438340;  1 drivers
+v0x561401430460_0 .net "Z", 0 0, L_0x5614014384a0;  1 drivers
+v0x561401430520_0 .net "nor1", 0 0, L_0x561401437e50;  1 drivers
+v0x5614014305e0_0 .net "nor2", 0 0, L_0x561401437f80;  1 drivers
+v0x5614014306a0_0 .net "nor3", 0 0, L_0x5614014380c0;  1 drivers
+v0x561401430760_0 .net "or1", 0 0, L_0x5614014382d0;  1 drivers
+v0x561401430820_0 .net "xor1", 0 0, L_0x561401437de0;  1 drivers
+v0x5614014308e0_0 .net "xor2", 0 0, L_0x561401437f10;  1 drivers
+S_0x561401430aa0 .scope module, "d3v" "dabble" 3 32, 4 1 0, S_0x56140140a900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+L_0x561401438bf0 .functor XOR 1, L_0x5614014393d0, L_0x5614014397a0, C4<0>, C4<0>;
+L_0x561401438c60 .functor NOR 1, L_0x5614014393d0, L_0x561401439560, C4<0>, C4<0>;
+L_0x561401438d20 .functor XOR 1, L_0x5614014393d0, L_0x561401439600, C4<0>, C4<0>;
+L_0x561401438d90 .functor NOR 1, L_0x561401438bf0, L_0x561401438d20, C4<0>, C4<0>;
+L_0x561401438ea0 .functor NOR 1, L_0x561401438d90, L_0x561401438c60, C4<0>, C4<0>;
+L_0x561401438fb0 .functor BUF 1, L_0x561401438ea0, C4<0>, C4<0>, C4<0>;
+L_0x561401439070 .functor OR 1, L_0x561401438bf0, L_0x561401438c60, C4<0>, C4<0>;
+L_0x5614014390e0 .functor NOR 1, L_0x561401439070, L_0x561401439600, C4<0>, C4<0>;
+L_0x561401439240 .functor AND 1, L_0x561401439070, L_0x561401438d20, C4<1>, C4<1>;
+L_0x5614014392b0 .functor XOR 1, L_0x561401438ea0, L_0x5614014397a0, C4<0>, C4<0>;
+v0x561401430d50_0 .net "A", 0 0, L_0x5614014393d0;  1 drivers
+v0x561401430e10_0 .net "B", 0 0, L_0x561401439560;  1 drivers
+v0x561401430ed0_0 .net "C", 0 0, L_0x561401439600;  1 drivers
+v0x561401430f70_0 .net "D", 0 0, L_0x5614014397a0;  1 drivers
+v0x561401431030_0 .net "E", 0 0, L_0x5614014392b0;  1 drivers
+v0x561401431140_0 .net "X", 0 0, L_0x561401438fb0;  1 drivers
+v0x561401431200_0 .net "Y", 0 0, L_0x5614014390e0;  1 drivers
+v0x5614014312c0_0 .net "Z", 0 0, L_0x561401439240;  1 drivers
+v0x561401431380_0 .net "nor1", 0 0, L_0x561401438c60;  1 drivers
+v0x5614014314d0_0 .net "nor2", 0 0, L_0x561401438d90;  1 drivers
+v0x561401431590_0 .net "nor3", 0 0, L_0x561401438ea0;  1 drivers
+v0x561401431650_0 .net "or1", 0 0, L_0x561401439070;  1 drivers
+v0x561401431710_0 .net "xor1", 0 0, L_0x561401438bf0;  1 drivers
+v0x5614014317d0_0 .net "xor2", 0 0, L_0x561401438d20;  1 drivers
+S_0x561401431990 .scope module, "d4w" "dabble" 3 41, 4 1 0, S_0x56140140a900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+L_0x561401439730 .functor XOR 1, L_0x561401436c90, L_0x56140143a360, C4<0>, C4<0>;
+L_0x561401439a00 .functor NOR 1, L_0x561401436c90, L_0x56140143a190, C4<0>, C4<0>;
+L_0x561401439b00 .functor XOR 1, L_0x561401436c90, L_0x56140143a230, C4<0>, C4<0>;
+L_0x561401439b70 .functor NOR 1, L_0x561401439730, L_0x561401439b00, C4<0>, C4<0>;
+L_0x561401439c60 .functor NOR 1, L_0x561401439b70, L_0x561401439a00, C4<0>, C4<0>;
+L_0x561401439d70 .functor BUF 1, L_0x561401439c60, C4<0>, C4<0>, C4<0>;
+L_0x561401439e30 .functor OR 1, L_0x561401439730, L_0x561401439a00, C4<0>, C4<0>;
+L_0x561401439ea0 .functor NOR 1, L_0x561401439e30, L_0x56140143a230, C4<0>, C4<0>;
+L_0x56140143a000 .functor AND 1, L_0x561401439e30, L_0x561401439b00, C4<1>, C4<1>;
+L_0x56140143a070 .functor XOR 1, L_0x561401439c60, L_0x56140143a360, C4<0>, C4<0>;
+v0x561401431c40_0 .net "A", 0 0, L_0x561401436c90;  alias, 1 drivers
+v0x561401431d20_0 .net "B", 0 0, L_0x56140143a190;  1 drivers
+v0x561401431de0_0 .net "C", 0 0, L_0x56140143a230;  1 drivers
+v0x561401431e80_0 .net "D", 0 0, L_0x56140143a360;  1 drivers
+v0x561401431f40_0 .net "E", 0 0, L_0x56140143a070;  1 drivers
+v0x561401432050_0 .net "X", 0 0, L_0x561401439d70;  1 drivers
+v0x561401432110_0 .net "Y", 0 0, L_0x561401439ea0;  1 drivers
+v0x5614014321d0_0 .net "Z", 0 0, L_0x56140143a000;  1 drivers
+v0x561401432290_0 .net "nor1", 0 0, L_0x561401439a00;  1 drivers
+v0x5614014323e0_0 .net "nor2", 0 0, L_0x561401439b70;  1 drivers
+v0x5614014324a0_0 .net "nor3", 0 0, L_0x561401439c60;  1 drivers
+v0x561401432560_0 .net "or1", 0 0, L_0x561401439e30;  1 drivers
+v0x561401432620_0 .net "xor1", 0 0, L_0x561401439730;  1 drivers
+v0x5614014326e0_0 .net "xor2", 0 0, L_0x561401439b00;  1 drivers
+S_0x5614014328a0 .scope module, "d5x" "dabble" 3 50, 4 1 0, S_0x56140140a900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+L_0x56140143a450 .functor XOR 1, L_0x56140143acc0, L_0x56140143adf0, C4<0>, C4<0>;
+L_0x56140143a4c0 .functor NOR 1, L_0x56140143acc0, L_0x56140143ae90, C4<0>, C4<0>;
+L_0x56140143a580 .functor XOR 1, L_0x56140143acc0, L_0x56140143af30, C4<0>, C4<0>;
+L_0x56140143a620 .functor NOR 1, L_0x56140143a450, L_0x56140143a580, C4<0>, C4<0>;
+L_0x56140143a790 .functor NOR 1, L_0x56140143a620, L_0x56140143a4c0, C4<0>, C4<0>;
+L_0x56140143a8a0 .functor BUF 1, L_0x56140143a790, C4<0>, C4<0>, C4<0>;
+L_0x56140143a960 .functor OR 1, L_0x56140143a450, L_0x56140143a4c0, C4<0>, C4<0>;
+L_0x56140143a9d0 .functor NOR 1, L_0x56140143a960, L_0x56140143af30, C4<0>, C4<0>;
+L_0x56140143ab30 .functor AND 1, L_0x56140143a960, L_0x56140143a580, C4<1>, C4<1>;
+L_0x56140143aba0 .functor XOR 1, L_0x56140143a790, L_0x56140143adf0, C4<0>, C4<0>;
+v0x561401432ba0_0 .net "A", 0 0, L_0x56140143acc0;  1 drivers
+v0x561401432c80_0 .net "B", 0 0, L_0x56140143ae90;  1 drivers
+v0x561401432d40_0 .net "C", 0 0, L_0x56140143af30;  1 drivers
+v0x561401432de0_0 .net "D", 0 0, L_0x56140143adf0;  1 drivers
+v0x561401432ea0_0 .net "E", 0 0, L_0x56140143aba0;  1 drivers
+v0x561401432fb0_0 .net "X", 0 0, L_0x56140143a8a0;  1 drivers
+v0x561401433070_0 .net "Y", 0 0, L_0x56140143a9d0;  1 drivers
+v0x561401433130_0 .net "Z", 0 0, L_0x56140143ab30;  1 drivers
+v0x5614014331f0_0 .net "nor1", 0 0, L_0x56140143a4c0;  1 drivers
+v0x561401433340_0 .net "nor2", 0 0, L_0x56140143a620;  1 drivers
+v0x561401433400_0 .net "nor3", 0 0, L_0x56140143a790;  1 drivers
+v0x5614014334c0_0 .net "or1", 0 0, L_0x56140143a960;  1 drivers
+v0x561401433580_0 .net "xor1", 0 0, L_0x56140143a450;  1 drivers
+v0x561401433640_0 .net "xor2", 0 0, L_0x56140143a580;  1 drivers
+S_0x561401433800 .scope module, "d6y" "dabble" 3 59, 4 1 0, S_0x56140140a900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+L_0x56140143b280 .functor XOR 1, L_0x56140143bac0, L_0x56140143be00, C4<0>, C4<0>;
+L_0x56140143b2f0 .functor NOR 1, L_0x56140143bac0, L_0x56140143bbf0, C4<0>, C4<0>;
+L_0x56140143b3b0 .functor XOR 1, L_0x56140143bac0, L_0x56140143bd60, C4<0>, C4<0>;
+L_0x56140143b420 .functor NOR 1, L_0x56140143b280, L_0x56140143b3b0, C4<0>, C4<0>;
+L_0x56140143b590 .functor NOR 1, L_0x56140143b420, L_0x56140143b2f0, C4<0>, C4<0>;
+L_0x56140143b6a0 .functor BUF 1, L_0x56140143b590, C4<0>, C4<0>, C4<0>;
+L_0x56140143b760 .functor OR 1, L_0x56140143b280, L_0x56140143b2f0, C4<0>, C4<0>;
+L_0x56140143b7d0 .functor NOR 1, L_0x56140143b760, L_0x56140143bd60, C4<0>, C4<0>;
+L_0x56140143b930 .functor AND 1, L_0x56140143b760, L_0x56140143b3b0, C4<1>, C4<1>;
+L_0x56140143b9a0 .functor XOR 1, L_0x56140143b590, L_0x56140143be00, C4<0>, C4<0>;
+v0x561401433ab0_0 .net "A", 0 0, L_0x56140143bac0;  1 drivers
+v0x561401433b90_0 .net "B", 0 0, L_0x56140143bbf0;  1 drivers
+v0x561401433c50_0 .net "C", 0 0, L_0x56140143bd60;  1 drivers
+v0x561401433cf0_0 .net "D", 0 0, L_0x56140143be00;  1 drivers
+v0x561401433db0_0 .net "E", 0 0, L_0x56140143b9a0;  1 drivers
+v0x561401433ec0_0 .net "X", 0 0, L_0x56140143b6a0;  1 drivers
+v0x561401433f80_0 .net "Y", 0 0, L_0x56140143b7d0;  1 drivers
+v0x561401434040_0 .net "Z", 0 0, L_0x56140143b930;  1 drivers
+v0x561401434100_0 .net "nor1", 0 0, L_0x56140143b2f0;  1 drivers
+v0x561401434250_0 .net "nor2", 0 0, L_0x56140143b420;  1 drivers
+v0x561401434310_0 .net "nor3", 0 0, L_0x56140143b590;  1 drivers
+v0x5614014343d0_0 .net "or1", 0 0, L_0x56140143b760;  1 drivers
+v0x561401434490_0 .net "xor1", 0 0, L_0x56140143b280;  1 drivers
+v0x561401434550_0 .net "xor2", 0 0, L_0x56140143b3b0;  1 drivers
+S_0x561401434710 .scope module, "d7z" "dabble" 3 68, 4 1 0, S_0x56140140a900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+L_0x56140143bfd0 .functor XOR 1, L_0x56140143c840, L_0x56140143cc30, C4<0>, C4<0>;
+L_0x56140143c040 .functor NOR 1, L_0x56140143c840, L_0x56140143c970, C4<0>, C4<0>;
+L_0x56140143c100 .functor XOR 1, L_0x56140143c840, L_0x56140143cb90, C4<0>, C4<0>;
+L_0x56140143c1a0 .functor NOR 1, L_0x56140143bfd0, L_0x56140143c100, C4<0>, C4<0>;
+L_0x56140143c310 .functor NOR 1, L_0x56140143c1a0, L_0x56140143c040, C4<0>, C4<0>;
+L_0x56140143c420 .functor BUF 1, L_0x56140143c310, C4<0>, C4<0>, C4<0>;
+L_0x56140143c4e0 .functor OR 1, L_0x56140143bfd0, L_0x56140143c040, C4<0>, C4<0>;
+L_0x56140143c550 .functor NOR 1, L_0x56140143c4e0, L_0x56140143cb90, C4<0>, C4<0>;
+L_0x56140143c6b0 .functor AND 1, L_0x56140143c4e0, L_0x56140143c100, C4<1>, C4<1>;
+L_0x56140143c720 .functor XOR 1, L_0x56140143c310, L_0x56140143cc30, C4<0>, C4<0>;
+v0x5614014349c0_0 .net "A", 0 0, L_0x56140143c840;  1 drivers
+v0x561401434aa0_0 .net "B", 0 0, L_0x56140143c970;  1 drivers
+v0x561401434b60_0 .net "C", 0 0, L_0x56140143cb90;  1 drivers
+v0x561401434c00_0 .net "D", 0 0, L_0x56140143cc30;  1 drivers
+v0x561401434cc0_0 .net "E", 0 0, L_0x56140143c720;  1 drivers
+v0x561401434dd0_0 .net "X", 0 0, L_0x56140143c420;  1 drivers
+v0x561401434e90_0 .net "Y", 0 0, L_0x56140143c550;  1 drivers
+v0x561401434f50_0 .net "Z", 0 0, L_0x56140143c6b0;  1 drivers
+v0x561401435010_0 .net "nor1", 0 0, L_0x56140143c040;  1 drivers
+v0x561401435160_0 .net "nor2", 0 0, L_0x56140143c1a0;  1 drivers
+v0x561401435220_0 .net "nor3", 0 0, L_0x56140143c310;  1 drivers
+v0x5614014352e0_0 .net "or1", 0 0, L_0x56140143c4e0;  1 drivers
+v0x5614014353a0_0 .net "xor1", 0 0, L_0x56140143bfd0;  1 drivers
+v0x561401435460_0 .net "xor2", 0 0, L_0x56140143c100;  1 drivers
+    .scope S_0x56140140d330;
+T_0 ;
+    %vpi_call 2 14 "$monitor", "Time: %0t | Binary: %b | BCD: %b (Hundreds: %d, Tens: %d, Ones: %d)", $time, v0x561401436b30_0, v0x561401436a70_0, &PV<v0x561401436a70_0, 8, 4>, &PV<v0x561401436a70_0, 4, 4>, &PV<v0x561401436a70_0, 0, 4> {0 0 0};
+    %vpi_call 2 16 "$dumpfile", "BinaryToBCD.vcd" {0 0 0};
+    %vpi_call 2 17 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0x561401436b30_0, 0, 8;
+    %delay 10, 0;
+    %pushi/vec4 10, 0, 8;
+    %store/vec4 v0x561401436b30_0, 0, 8;
+    %delay 10, 0;
+    %pushi/vec4 42, 0, 8;
+    %store/vec4 v0x561401436b30_0, 0, 8;
+    %delay 10, 0;
+    %pushi/vec4 99, 0, 8;
+    %store/vec4 v0x561401436b30_0, 0, 8;
+    %delay 10, 0;
+    %pushi/vec4 153, 0, 8;
+    %store/vec4 v0x561401436b30_0, 0, 8;
+    %delay 10, 0;
+    %pushi/vec4 255, 0, 8;
+    %store/vec4 v0x561401436b30_0, 0, 8;
+    %delay 10, 0;
+    %vpi_call 2 38 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 5;
+    "N/A";
+    "<interactive>";
+    "BinaryToBCDTB.v";
+    "BinaryToBCD.v";
+    "dabble.v";
--- a/verilog/ALU0.2/binarytobcdZone.Identifier
+++ b/verilog/ALU0.2/binarytobcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/dabble
+++ b/verilog/ALU0.2/dabble
@@ -0,0 +1,52 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x5621d16e7df0 .scope module, "dabble" "dabble" 2 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "C";
+    .port_info 3 /INPUT 1 "D";
+    .port_info 4 /OUTPUT 1 "X";
+    .port_info 5 /OUTPUT 1 "Y";
+    .port_info 6 /OUTPUT 1 "Z";
+    .port_info 7 /OUTPUT 1 "E";
+o0x7f27d282c018 .functor BUFZ 1, C4<z>; HiZ drive
+o0x7f27d282c0a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0x5621d1732e70 .functor XOR 1, o0x7f27d282c018, o0x7f27d282c0a8, C4<0>, C4<0>;
+o0x7f27d282c048 .functor BUFZ 1, C4<z>; HiZ drive
+L_0x5621d1732f60 .functor NOR 1, o0x7f27d282c018, o0x7f27d282c048, C4<0>, C4<0>;
+o0x7f27d282c078 .functor BUFZ 1, C4<z>; HiZ drive
+L_0x5621d1733000 .functor XOR 1, o0x7f27d282c018, o0x7f27d282c078, C4<0>, C4<0>;
+L_0x5621d17330d0 .functor NOR 1, L_0x5621d1732e70, L_0x5621d1733000, C4<0>, C4<0>;
+L_0x5621d1733240 .functor NOR 1, L_0x5621d17330d0, L_0x5621d1732f60, C4<0>, C4<0>;
+L_0x5621d1733350 .functor BUF 1, L_0x5621d1733240, C4<0>, C4<0>, C4<0>;
+L_0x5621d1733450 .functor OR 1, L_0x5621d1732e70, L_0x5621d1732f60, C4<0>, C4<0>;
+L_0x5621d17334c0 .functor NOR 1, L_0x5621d1733450, o0x7f27d282c078, C4<0>, C4<0>;
+L_0x5621d1733620 .functor AND 1, L_0x5621d1733450, L_0x5621d1733000, C4<1>, C4<1>;
+L_0x5621d1733690 .functor XOR 1, L_0x5621d1733240, o0x7f27d282c0a8, C4<0>, C4<0>;
+v0x5621d16e8050_0 .net "A", 0 0, o0x7f27d282c018;  0 drivers
+v0x5621d1732380_0 .net "B", 0 0, o0x7f27d282c048;  0 drivers
+v0x5621d1732440_0 .net "C", 0 0, o0x7f27d282c078;  0 drivers
+v0x5621d17324e0_0 .net "D", 0 0, o0x7f27d282c0a8;  0 drivers
+v0x5621d17325a0_0 .net "E", 0 0, L_0x5621d1733690;  1 drivers
+v0x5621d17326b0_0 .net "X", 0 0, L_0x5621d1733350;  1 drivers
+v0x5621d1732770_0 .net "Y", 0 0, L_0x5621d17334c0;  1 drivers
+v0x5621d1732830_0 .net "Z", 0 0, L_0x5621d1733620;  1 drivers
+v0x5621d17328f0_0 .net "nor1", 0 0, L_0x5621d1732f60;  1 drivers
+v0x5621d17329b0_0 .net "nor2", 0 0, L_0x5621d17330d0;  1 drivers
+v0x5621d1732a70_0 .net "nor3", 0 0, L_0x5621d1733240;  1 drivers
+v0x5621d1732b30_0 .net "or1", 0 0, L_0x5621d1733450;  1 drivers
+v0x5621d1732bf0_0 .net "xor1", 0 0, L_0x5621d1732e70;  1 drivers
+v0x5621d1732cb0_0 .net "xor2", 0 0, L_0x5621d1733000;  1 drivers
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "dabble.v";
--- a/verilog/ALU0.2/dabble.v
+++ b/verilog/ALU0.2/dabble.v
@@ -0,0 +1,22 @@
+module dabble (
+    input A, B, C, D,
+    output X, Y, Z, E
+);
+
+wire xor1, nor1, xor2, nor2, nor3, or1;
+
+xor xo1 (xor1, A, D);
+nor no1 (nor1, A, B);
+xor xo2 (xor2, A, C);
+
+nor no2 (nor2, xor1, xor2);
+
+nor no3 (nor3, nor2, nor1);
+buf bu1 (X, nor3);
+or o1 (or1, xor1, nor1);
+
+nor no4 (Y, or1, C);
+and an1 (Z, or1, xor2);
+xor xo3 (E, nor3, D);
+
+endmodule
--- a/verilog/ALU0.2/dabble.vZone.Identifier
+++ b/verilog/ALU0.2/dabble.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/dabbleZone.Identifier
+++ b/verilog/ALU0.2/dabbleZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/divider.v
+++ b/verilog/ALU0.2/divider.v
@@ -0,0 +1,11 @@
+module divider (
+    input [3:0] D,
+    input [1:0] d,
+    output [2:0] R,
+    output [3:0] Q
+);
+
+wire s1,y1,c1;
+
+dividerpu d1 (.A(D[3]), .B(d[0]), .Cin(1'b1), .S(s1), .Y(y1), .COut(c1));
+dividerpu d2 (.A(1'b0), .B(d[1]), .Cin(c1), .S(s1), .Y(y1), .COut(c1));
--- a/verilog/ALU0.2/divider.vZone.Identifier
+++ b/verilog/ALU0.2/divider.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/fulladder.v
+++ b/verilog/ALU0.2/fulladder.v
@@ -0,0 +1,12 @@
+module fulladder (
+    input A, B, Carry,
+    output Sum, CarryO
+);
+
+wire xor1, and1, and2;
+
+halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
+halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
+or o1 (CarryO, and1, and2);
+
+endmodule
--- a/verilog/ALU0.2/fulladder.vZone.Identifier
+++ b/verilog/ALU0.2/fulladder.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/fullsubtraction.v
+++ b/verilog/ALU0.2/fullsubtraction.v
@@ -0,0 +1,12 @@
+module fullsubtraction (
+    input A, B, BorrowIN,
+    output Difference, BorrowOut
+);
+
+wire tempD, tempB1, tempB2;
+
+halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
+halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
+or o1 (BorrowOut, tempB1, tempB2);
+
+endmodule
--- a/verilog/ALU0.2/fullsubtraction.vZone.Identifier
+++ b/verilog/ALU0.2/fullsubtraction.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/halfadder.v
+++ b/verilog/ALU0.2/halfadder.v
@@ -0,0 +1,9 @@
+module halfadder (
+    input A, B,
+    output Sum, Carry
+);
+
+and a1 (Carry, A, B);
+xor xo1 (Sum, A, B);
+
+endmodule
--- a/verilog/ALU0.2/halfadder.vZone.Identifier
+++ b/verilog/ALU0.2/halfadder.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/halfsubtraction.v
+++ b/verilog/ALU0.2/halfsubtraction.v
@@ -0,0 +1,12 @@
+module halfsubtraction (
+    input A, B,
+    output Difference, Borrow
+);
+
+wire notA;
+
+xor xo1 (Difference, A, B);
+not a1 (notA, A);
+and an1 (Borrow, notA, B);
+
+endmodule
--- a/verilog/ALU0.2/halfsubtraction.vZone.Identifier
+++ b/verilog/ALU0.2/halfsubtraction.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/logicUnit
+++ b/verilog/ALU0.2/logicUnit
@@ -0,0 +1,288 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x56004b80baa0 .scope module, "logicUnitTB" "logicUnitTB" 2 1;
+ .timescale 0 0;
+v0x56004b83a150_0 .var "A", 3 0;
+v0x56004b83a230_0 .var "B", 3 0;
+v0x56004b83a300_0 .var "opCode", 2 0;
+v0x56004b83a400_0 .net "resultA", 3 0, L_0x56004b83d920;  1 drivers
+v0x56004b83a4d0_0 .net "resultO", 3 0, L_0x56004b83ec00;  1 drivers
+v0x56004b83a570_0 .net "resultX", 3 0, L_0x56004b83fe60;  1 drivers
+S_0x56004b80bc30 .scope module, "uut" "logicUnit" 2 7, 3 1 0, S_0x56004b80baa0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 3 "opCode";
+    .port_info 1 /INPUT 4 "A";
+    .port_info 2 /INPUT 4 "B";
+    .port_info 3 /OUTPUT 4 "resultA";
+    .port_info 4 /OUTPUT 4 "resultO";
+    .port_info 5 /OUTPUT 4 "resultX";
+L_0x56004b83a640 .functor AND 1, L_0x56004b83a740, L_0x56004b83a880, C4<1>, C4<1>;
+L_0x56004b83a9c0 .functor AND 1, L_0x56004b83aa30, L_0x56004b83ab20, C4<1>, C4<1>;
+L_0x56004b83ac40 .functor AND 1, L_0x56004b83acb0, L_0x56004b83ada0, C4<1>, C4<1>;
+L_0x56004b83afc0 .functor AND 1, L_0x56004b83b0b0, L_0x56004b83b1f0, C4<1>, C4<1>;
+L_0x56004b83b2e0 .functor OR 1, L_0x56004b83b350, L_0x56004b83b4a0, C4<0>, C4<0>;
+L_0x56004b83b540 .functor OR 1, L_0x56004b83b5f0, L_0x56004b83b750, C4<0>, C4<0>;
+L_0x56004b83b840 .functor OR 1, L_0x56004b83b8b0, L_0x56004b83ba20, C4<0>, C4<0>;
+L_0x56004b83b6e0 .functor OR 1, L_0x56004b83bdd0, L_0x56004b83bec0, C4<0>, C4<0>;
+L_0x56004b83c050 .functor XOR 1, L_0x56004b83c0c0, L_0x56004b83c1b0, C4<0>, C4<0>;
+L_0x56004b83c350 .functor XOR 1, L_0x56004b83bfb0, L_0x56004b83c450, C4<0>, C4<0>;
+L_0x56004b83c600 .functor XOR 1, L_0x56004b83c6a0, L_0x56004b83c790, C4<0>, C4<0>;
+L_0x56004b83cae0 .functor XOR 1, L_0x56004b83cc10, L_0x56004b83cde0, C4<0>, C4<0>;
+L_0x56004b83ced0 .functor AND 1, L_0x56004b83cf40, L_0x56004b83d170, C4<1>, C4<1>;
+L_0x56004b83d2b0 .functor AND 1, L_0x56004b83d3a0, L_0x56004b83d590, C4<1>, C4<1>;
+L_0x56004b83cba0 .functor AND 1, L_0x56004b83d680, L_0x56004b83d880, C4<1>, C4<1>;
+L_0x56004b83dbd0 .functor AND 1, L_0x56004b83dd20, L_0x56004b83de10, C4<1>, C4<1>;
+L_0x56004b83e030 .functor AND 1, L_0x56004b83e0a0, L_0x56004b83e190, C4<1>, C4<1>;
+L_0x56004b83e410 .functor AND 1, L_0x56004b83e520, L_0x56004b83e610, C4<1>, C4<1>;
+L_0x56004b83e850 .functor AND 1, L_0x56004b83e8c0, L_0x56004b83e9b0, C4<1>, C4<1>;
+L_0x56004b83ed90 .functor AND 1, L_0x56004b83e480, L_0x56004b83f0c0, C4<1>, C4<1>;
+L_0x56004b83f1b0 .functor AND 1, L_0x56004b83f220, L_0x56004b83f490, C4<1>, C4<1>;
+L_0x56004b83f5d0 .functor AND 1, L_0x56004b83f700, L_0x56004b83f980, C4<1>, C4<1>;
+L_0x56004b83fa70 .functor AND 1, L_0x56004b83fae0, L_0x56004b83fd70, C4<1>, C4<1>;
+L_0x56004b8401a0 .functor AND 1, L_0x56004b840330, L_0x56004b840420, C4<1>, C4<1>;
+v0x56004b7c9cf0_0 .net "A", 3 0, v0x56004b83a150_0;  1 drivers
+v0x56004b835650_0 .net "B", 3 0, v0x56004b83a230_0;  1 drivers
+v0x56004b835730_0 .net *"_ivl_0", 0 0, L_0x56004b83a640;  1 drivers
+v0x56004b8357f0_0 .net *"_ivl_100", 0 0, L_0x56004b83e030;  1 drivers
+v0x56004b8358d0_0 .net *"_ivl_103", 0 0, L_0x56004b83e0a0;  1 drivers
+v0x56004b835a00_0 .net *"_ivl_105", 0 0, L_0x56004b83e190;  1 drivers
+v0x56004b835ae0_0 .net *"_ivl_106", 0 0, L_0x56004b83e410;  1 drivers
+v0x56004b835bc0_0 .net *"_ivl_109", 0 0, L_0x56004b83e520;  1 drivers
+v0x56004b835ca0_0 .net *"_ivl_11", 0 0, L_0x56004b83ab20;  1 drivers
+v0x56004b835d80_0 .net *"_ivl_111", 0 0, L_0x56004b83e610;  1 drivers
+v0x56004b835e60_0 .net *"_ivl_112", 0 0, L_0x56004b83e850;  1 drivers
+v0x56004b835f40_0 .net *"_ivl_115", 0 0, L_0x56004b83e8c0;  1 drivers
+v0x56004b836020_0 .net *"_ivl_117", 0 0, L_0x56004b83e9b0;  1 drivers
+v0x56004b836100_0 .net *"_ivl_118", 0 0, L_0x56004b83ed90;  1 drivers
+v0x56004b8361e0_0 .net *"_ivl_12", 0 0, L_0x56004b83ac40;  1 drivers
+v0x56004b8362c0_0 .net *"_ivl_122", 0 0, L_0x56004b83e480;  1 drivers
+v0x56004b8363a0_0 .net *"_ivl_124", 0 0, L_0x56004b83f0c0;  1 drivers
+v0x56004b836480_0 .net *"_ivl_125", 0 0, L_0x56004b83f1b0;  1 drivers
+v0x56004b836560_0 .net *"_ivl_128", 0 0, L_0x56004b83f220;  1 drivers
+v0x56004b836640_0 .net *"_ivl_130", 0 0, L_0x56004b83f490;  1 drivers
+v0x56004b836720_0 .net *"_ivl_131", 0 0, L_0x56004b83f5d0;  1 drivers
+v0x56004b836800_0 .net *"_ivl_134", 0 0, L_0x56004b83f700;  1 drivers
+v0x56004b8368e0_0 .net *"_ivl_136", 0 0, L_0x56004b83f980;  1 drivers
+v0x56004b8369c0_0 .net *"_ivl_137", 0 0, L_0x56004b83fa70;  1 drivers
+v0x56004b836aa0_0 .net *"_ivl_140", 0 0, L_0x56004b83fae0;  1 drivers
+v0x56004b836b80_0 .net *"_ivl_142", 0 0, L_0x56004b83fd70;  1 drivers
+v0x56004b836c60_0 .net *"_ivl_143", 0 0, L_0x56004b8401a0;  1 drivers
+v0x56004b836d40_0 .net *"_ivl_147", 0 0, L_0x56004b840330;  1 drivers
+v0x56004b836e20_0 .net *"_ivl_149", 0 0, L_0x56004b840420;  1 drivers
+v0x56004b836f00_0 .net *"_ivl_15", 0 0, L_0x56004b83acb0;  1 drivers
+v0x56004b836fe0_0 .net *"_ivl_17", 0 0, L_0x56004b83ada0;  1 drivers
+v0x56004b8370c0_0 .net *"_ivl_18", 0 0, L_0x56004b83afc0;  1 drivers
+v0x56004b8371a0_0 .net *"_ivl_22", 0 0, L_0x56004b83b0b0;  1 drivers
+v0x56004b837280_0 .net *"_ivl_24", 0 0, L_0x56004b83b1f0;  1 drivers
+v0x56004b837360_0 .net *"_ivl_25", 0 0, L_0x56004b83b2e0;  1 drivers
+v0x56004b837440_0 .net *"_ivl_28", 0 0, L_0x56004b83b350;  1 drivers
+v0x56004b837520_0 .net *"_ivl_3", 0 0, L_0x56004b83a740;  1 drivers
+v0x56004b837600_0 .net *"_ivl_30", 0 0, L_0x56004b83b4a0;  1 drivers
+v0x56004b8376e0_0 .net *"_ivl_31", 0 0, L_0x56004b83b540;  1 drivers
+v0x56004b8377c0_0 .net *"_ivl_34", 0 0, L_0x56004b83b5f0;  1 drivers
+v0x56004b8378a0_0 .net *"_ivl_36", 0 0, L_0x56004b83b750;  1 drivers
+v0x56004b837980_0 .net *"_ivl_37", 0 0, L_0x56004b83b840;  1 drivers
+v0x56004b837a60_0 .net *"_ivl_40", 0 0, L_0x56004b83b8b0;  1 drivers
+v0x56004b837b40_0 .net *"_ivl_42", 0 0, L_0x56004b83ba20;  1 drivers
+v0x56004b837c20_0 .net *"_ivl_43", 0 0, L_0x56004b83b6e0;  1 drivers
+v0x56004b837d00_0 .net *"_ivl_47", 0 0, L_0x56004b83bdd0;  1 drivers
+v0x56004b837de0_0 .net *"_ivl_49", 0 0, L_0x56004b83bec0;  1 drivers
+v0x56004b837ec0_0 .net *"_ivl_5", 0 0, L_0x56004b83a880;  1 drivers
+v0x56004b837fa0_0 .net *"_ivl_50", 0 0, L_0x56004b83c050;  1 drivers
+v0x56004b838080_0 .net *"_ivl_53", 0 0, L_0x56004b83c0c0;  1 drivers
+v0x56004b838160_0 .net *"_ivl_55", 0 0, L_0x56004b83c1b0;  1 drivers
+v0x56004b838240_0 .net *"_ivl_56", 0 0, L_0x56004b83c350;  1 drivers
+v0x56004b838320_0 .net *"_ivl_59", 0 0, L_0x56004b83bfb0;  1 drivers
+v0x56004b838400_0 .net *"_ivl_6", 0 0, L_0x56004b83a9c0;  1 drivers
+v0x56004b8384e0_0 .net *"_ivl_61", 0 0, L_0x56004b83c450;  1 drivers
+v0x56004b8385c0_0 .net *"_ivl_62", 0 0, L_0x56004b83c600;  1 drivers
+v0x56004b8386a0_0 .net *"_ivl_65", 0 0, L_0x56004b83c6a0;  1 drivers
+v0x56004b838780_0 .net *"_ivl_67", 0 0, L_0x56004b83c790;  1 drivers
+v0x56004b838860_0 .net *"_ivl_68", 0 0, L_0x56004b83cae0;  1 drivers
+v0x56004b838940_0 .net *"_ivl_72", 0 0, L_0x56004b83cc10;  1 drivers
+v0x56004b838a20_0 .net *"_ivl_74", 0 0, L_0x56004b83cde0;  1 drivers
+v0x56004b838b00_0 .net *"_ivl_75", 0 0, L_0x56004b83ced0;  1 drivers
+v0x56004b838be0_0 .net *"_ivl_78", 0 0, L_0x56004b83cf40;  1 drivers
+v0x56004b838cc0_0 .net *"_ivl_80", 0 0, L_0x56004b83d170;  1 drivers
+v0x56004b838da0_0 .net *"_ivl_81", 0 0, L_0x56004b83d2b0;  1 drivers
+v0x56004b839290_0 .net *"_ivl_84", 0 0, L_0x56004b83d3a0;  1 drivers
+v0x56004b839370_0 .net *"_ivl_86", 0 0, L_0x56004b83d590;  1 drivers
+v0x56004b839450_0 .net *"_ivl_87", 0 0, L_0x56004b83cba0;  1 drivers
+v0x56004b839530_0 .net *"_ivl_9", 0 0, L_0x56004b83aa30;  1 drivers
+v0x56004b839610_0 .net *"_ivl_90", 0 0, L_0x56004b83d680;  1 drivers
+v0x56004b8396f0_0 .net *"_ivl_92", 0 0, L_0x56004b83d880;  1 drivers
+v0x56004b8397d0_0 .net *"_ivl_93", 0 0, L_0x56004b83dbd0;  1 drivers
+v0x56004b8398b0_0 .net *"_ivl_97", 0 0, L_0x56004b83dd20;  1 drivers
+v0x56004b839990_0 .net *"_ivl_99", 0 0, L_0x56004b83de10;  1 drivers
+v0x56004b839a70_0 .net "and1", 3 0, L_0x56004b83ae80;  1 drivers
+v0x56004b839b50_0 .net "opCode", 2 0, v0x56004b83a300_0;  1 drivers
+v0x56004b839c30_0 .net "or1", 3 0, L_0x56004b83bb10;  1 drivers
+v0x56004b839d10_0 .net "resultA", 3 0, L_0x56004b83d920;  alias, 1 drivers
+v0x56004b839df0_0 .net "resultO", 3 0, L_0x56004b83ec00;  alias, 1 drivers
+v0x56004b839ed0_0 .net "resultX", 3 0, L_0x56004b83fe60;  alias, 1 drivers
+v0x56004b839fb0_0 .net "xor1", 3 0, L_0x56004b83c950;  1 drivers
+L_0x56004b83a740 .part v0x56004b83a150_0, 0, 1;
+L_0x56004b83a880 .part v0x56004b83a230_0, 0, 1;
+L_0x56004b83aa30 .part v0x56004b83a150_0, 1, 1;
+L_0x56004b83ab20 .part v0x56004b83a230_0, 1, 1;
+L_0x56004b83acb0 .part v0x56004b83a150_0, 2, 1;
+L_0x56004b83ada0 .part v0x56004b83a230_0, 2, 1;
+L_0x56004b83ae80 .concat8 [ 1 1 1 1], L_0x56004b83a640, L_0x56004b83a9c0, L_0x56004b83ac40, L_0x56004b83afc0;
+L_0x56004b83b0b0 .part v0x56004b83a150_0, 3, 1;
+L_0x56004b83b1f0 .part v0x56004b83a230_0, 3, 1;
+L_0x56004b83b350 .part v0x56004b83a150_0, 0, 1;
+L_0x56004b83b4a0 .part v0x56004b83a230_0, 0, 1;
+L_0x56004b83b5f0 .part v0x56004b83a150_0, 1, 1;
+L_0x56004b83b750 .part v0x56004b83a230_0, 1, 1;
+L_0x56004b83b8b0 .part v0x56004b83a150_0, 2, 1;
+L_0x56004b83ba20 .part v0x56004b83a230_0, 2, 1;
+L_0x56004b83bb10 .concat8 [ 1 1 1 1], L_0x56004b83b2e0, L_0x56004b83b540, L_0x56004b83b840, L_0x56004b83b6e0;
+L_0x56004b83bdd0 .part v0x56004b83a150_0, 3, 1;
+L_0x56004b83bec0 .part v0x56004b83a230_0, 3, 1;
+L_0x56004b83c0c0 .part v0x56004b83a150_0, 0, 1;
+L_0x56004b83c1b0 .part v0x56004b83a230_0, 0, 1;
+L_0x56004b83bfb0 .part v0x56004b83a150_0, 1, 1;
+L_0x56004b83c450 .part v0x56004b83a230_0, 1, 1;
+L_0x56004b83c6a0 .part v0x56004b83a150_0, 2, 1;
+L_0x56004b83c790 .part v0x56004b83a230_0, 2, 1;
+L_0x56004b83c950 .concat8 [ 1 1 1 1], L_0x56004b83c050, L_0x56004b83c350, L_0x56004b83c600, L_0x56004b83cae0;
+L_0x56004b83cc10 .part v0x56004b83a150_0, 3, 1;
+L_0x56004b83cde0 .part v0x56004b83a230_0, 3, 1;
+L_0x56004b83cf40 .part v0x56004b83a300_0, 0, 1;
+L_0x56004b83d170 .part L_0x56004b83ae80, 0, 1;
+L_0x56004b83d3a0 .part v0x56004b83a300_0, 0, 1;
+L_0x56004b83d590 .part L_0x56004b83ae80, 1, 1;
+L_0x56004b83d680 .part v0x56004b83a300_0, 0, 1;
+L_0x56004b83d880 .part L_0x56004b83ae80, 2, 1;
+L_0x56004b83d920 .concat8 [ 1 1 1 1], L_0x56004b83ced0, L_0x56004b83d2b0, L_0x56004b83cba0, L_0x56004b83dbd0;
+L_0x56004b83dd20 .part v0x56004b83a300_0, 0, 1;
+L_0x56004b83de10 .part L_0x56004b83ae80, 3, 1;
+L_0x56004b83e0a0 .part v0x56004b83a300_0, 1, 1;
+L_0x56004b83e190 .part L_0x56004b83bb10, 0, 1;
+L_0x56004b83e520 .part v0x56004b83a300_0, 1, 1;
+L_0x56004b83e610 .part L_0x56004b83bb10, 1, 1;
+L_0x56004b83e8c0 .part v0x56004b83a300_0, 1, 1;
+L_0x56004b83e9b0 .part L_0x56004b83bb10, 2, 1;
+L_0x56004b83ec00 .concat8 [ 1 1 1 1], L_0x56004b83e030, L_0x56004b83e410, L_0x56004b83e850, L_0x56004b83ed90;
+L_0x56004b83e480 .part v0x56004b83a300_0, 1, 1;
+L_0x56004b83f0c0 .part L_0x56004b83bb10, 3, 1;
+L_0x56004b83f220 .part v0x56004b83a300_0, 2, 1;
+L_0x56004b83f490 .part L_0x56004b83c950, 0, 1;
+L_0x56004b83f700 .part v0x56004b83a300_0, 2, 1;
+L_0x56004b83f980 .part L_0x56004b83c950, 1, 1;
+L_0x56004b83fae0 .part v0x56004b83a300_0, 2, 1;
+L_0x56004b83fd70 .part L_0x56004b83c950, 2, 1;
+L_0x56004b83fe60 .concat8 [ 1 1 1 1], L_0x56004b83f1b0, L_0x56004b83f5d0, L_0x56004b83fa70, L_0x56004b8401a0;
+L_0x56004b840330 .part v0x56004b83a300_0, 2, 1;
+L_0x56004b840420 .part L_0x56004b83c950, 3, 1;
+    .scope S_0x56004b80baa0;
+T_0 ;
+    %vpi_call 2 17 "$dumpfile", "logicUnit.vcd" {0 0 0};
+    %vpi_call 2 18 "$dumpvars" {0 0 0};
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 1, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 1, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 3, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 1, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 9, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 9, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 1, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 5, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 9, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 5, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 1, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 5, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 5, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 5, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v0x56004b83a300_0, 0, 3;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x56004b83a150_0, 0, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x56004b83a230_0, 0, 4;
+    %delay 2, 0;
+    %vpi_call 2 34 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "logicUnitTB.v";
+    "logicUnit.v";
--- a/verilog/ALU0.2/logicUnit.v
+++ b/verilog/ALU0.2/logicUnit.v
@@ -0,0 +1,39 @@
+module logicUnit (
+    input [2:0] opCode,
+    input [3:0] A, B,
+    output [3:0] resultA, resultO, resultX
+);
+
+wire [3:0] and1, or1, xor1;
+
+and a01 (and1[0], A[0], B[0]);
+and a02 (and1[1], A[1], B[1]);
+and a03 (and1[2], A[2], B[2]);
+and a04 (and1[3], A[3], B[3]);
+
+or o01 (or1[0], A[0], B[0]);
+or o02 (or1[1], A[1], B[1]);
+or o03 (or1[2], A[2], B[2]);
+or o04 (or1[3], A[3], B[3]);
+
+xor xor01 (xor1[0], A[0], B[0]);
+xor xor02 (xor1[1], A[1], B[1]);
+xor xor03 (xor1[2], A[2], B[2]);
+xor xor04 (xor1[3], A[3], B[3]);
+
+and a_o1 (resultA[0], opCode[0], and1[0]);
+and a_o2 (resultA[1], opCode[0], and1[1]);
+and a_o3 (resultA[2], opCode[0], and1[2]);
+and a_o4 (resultA[3], opCode[0], and1[3]);
+
+and o_o1 (resultO[0], opCode[1], or1[0]);
+and o_o2 (resultO[1], opCode[1], or1[1]);
+and o_o3 (resultO[2], opCode[1], or1[2]);
+and o_o4 (resultO[3], opCode[1], or1[3]);
+
+and x_o1 (resultX[0], opCode[2], xor1[0]);
+and x_o2 (resultX[1], opCode[2], xor1[1]);
+and x_o3 (resultX[2], opCode[2], xor1[2]);
+and x_o4 (resultX[3], opCode[2], xor1[3]);
+
+endmodule
--- a/verilog/ALU0.2/logicUnit.vcd
+++ b/verilog/ALU0.2/logicUnit.vcd
@@ -0,0 +1,150 @@
+$date
+	Sat Dec 14 03:32:40 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module logicUnitTB $end
+$var wire 4 ! resultX [3:0] $end
+$var wire 4 " resultO [3:0] $end
+$var wire 4 # resultA [3:0] $end
+$var reg 4 $ A [3:0] $end
+$var reg 4 % B [3:0] $end
+$var reg 3 & opCode [2:0] $end
+$scope module uut $end
+$var wire 4 ' A [3:0] $end
+$var wire 4 ( B [3:0] $end
+$var wire 3 ) opCode [2:0] $end
+$var wire 4 * xor1 [3:0] $end
+$var wire 4 + resultX [3:0] $end
+$var wire 4 , resultO [3:0] $end
+$var wire 4 - resultA [3:0] $end
+$var wire 4 . or1 [3:0] $end
+$var wire 4 / and1 [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b1 /
+b1 .
+b1 -
+b0 ,
+b0 +
+b0 *
+b1 )
+b1 (
+b1 '
+b1 &
+b1 %
+b1 $
+b1 #
+b0 "
+b0 !
+$end
+#2
+b11 .
+b10 *
+b11 $
+b11 '
+#4
+b1001 #
+b1001 -
+b1001 /
+b1001 .
+b0 *
+b1001 %
+b1001 (
+b1001 $
+b1001 '
+#6
+b1111 #
+b1111 -
+b1111 /
+b1111 .
+b1111 %
+b1111 (
+b1111 $
+b1111 '
+#8
+b0 #
+b0 -
+b0 /
+b0 .
+b0 %
+b0 (
+b0 $
+b0 '
+#10
+b101 "
+b101 ,
+b100 *
+b1 /
+b101 .
+b101 %
+b101 (
+b1 $
+b1 '
+b10 &
+b10 )
+#12
+b1101 "
+b1101 ,
+b1101 .
+b1100 *
+b1001 $
+b1001 '
+#14
+b1111 "
+b1111 ,
+b1111 .
+b1110 *
+b1111 %
+b1111 (
+b1 $
+b1 '
+#16
+b101 "
+b101 ,
+b101 .
+b0 /
+b101 *
+b101 %
+b101 (
+b0 $
+b0 '
+#18
+b0 "
+b0 ,
+b101 !
+b101 +
+b100 &
+b100 )
+#20
+b0 !
+b0 +
+b0 .
+b0 *
+b0 %
+b0 (
+#22
+b101 !
+b101 +
+b101 .
+b101 *
+b101 %
+b101 (
+#24
+b0 !
+b0 +
+b1111 /
+b1111 .
+b0 *
+b1111 %
+b1111 (
+b1111 $
+b1111 '
+#26
--- a/verilog/ALU0.2/logicUnit.vcdZone.Identifier
+++ b/verilog/ALU0.2/logicUnit.vcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/logicUnit.vZone.Identifier
+++ b/verilog/ALU0.2/logicUnit.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/logicUnitTB.v
+++ b/verilog/ALU0.2/logicUnitTB.v
@@ -0,0 +1,37 @@
+module logicUnitTB ();
+
+reg [2:0] opCode;
+reg [3:0] A, B;
+wire [3:0] resultA, resultO, resultX;
+
+logicUnit uut (
+    .opCode(opCode),
+    .A(A),
+    .B(B),
+    .resultA(resultA),
+    .resultO(resultO),
+    .resultX(resultX)
+);
+
+initial begin
+    $dumpfile("logicUnit.vcd");
+    $dumpvars;
+    opCode = 3'b001; A = 4'b0001; B = 4'b0001; #2;
+    opCode = 3'b001; A = 4'b0011; B = 4'b0001; #2;
+    opCode = 3'b001; A = 4'b1001; B = 4'b1001; #2;
+    opCode = 3'b001; A = 4'b1111; B = 4'b1111; #2;
+    opCode = 3'b001; A = 4'b0000; B = 4'b0000; #2;
+
+    opCode = 3'b010; A = 4'b0001; B = 4'b0101; #2;
+    opCode = 3'b010; A = 4'b1001; B = 4'b0101; #2;
+    opCode = 3'b010; A = 4'b0001; B = 4'b1111; #2;
+    opCode = 3'b010; A = 4'b0000; B = 4'b0101; #2;
+
+    opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
+    opCode = 3'b100; A = 4'b0000; B = 4'b0000; #2;
+    opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
+    opCode = 3'b100; A = 4'b1111; B = 4'b1111; #2;
+    $finish;
+end
+
+endmodule
--- a/verilog/ALU0.2/logicUnitTB.vZone.Identifier
+++ b/verilog/ALU0.2/logicUnitTB.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/logicUnitZone.Identifier
+++ b/verilog/ALU0.2/logicUnitZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/multiplier
+++ b/verilog/ALU0.2/multiplier
@@ -0,0 +1,957 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55f30e07afd0 .scope module, "multiplierTB" "multiplierTB" 2 1;
+ .timescale 0 0;
+v0x55f30e0dc920_0 .var "A", 3 0;
+v0x55f30e0dc9e0_0 .var "B", 3 0;
+v0x55f30e0dca80_0 .net "Y", 7 0, L_0x55f30e0eaf60;  1 drivers
+S_0x55f30e070c90 .scope module, "uut" "multiplier" 2 5, 3 1 0, S_0x55f30e07afd0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /OUTPUT 8 "Y";
+L_0x55f30e0dcb20 .functor AND 1, L_0x55f30e0dcb90, L_0x55f30e0dccd0, C4<1>, C4<1>;
+L_0x55f30e0dce10 .functor AND 1, L_0x55f30e0dce80, L_0x55f30e0dcf70, C4<1>, C4<1>;
+L_0x55f30e0dd060 .functor AND 1, L_0x55f30e0dd0d0, L_0x55f30e0dd1c0, C4<1>, C4<1>;
+L_0x55f30e0dd330 .functor AND 1, L_0x55f30e0dd3d0, L_0x55f30e0dd470, C4<1>, C4<1>;
+L_0x7f5d71fc0018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0dd740 .functor NOT 1, L_0x7f5d71fc0018, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0dd850 .functor AND 1, L_0x55f30e0dd900, L_0x55f30e0dda50, C4<1>, C4<1>;
+L_0x55f30e0ddaf0 .functor AND 1, L_0x55f30e0ddb60, L_0x55f30e0ddcc0, C4<1>, C4<1>;
+L_0x55f30e0dddb0 .functor AND 1, L_0x55f30e0dde70, L_0x55f30e0ddfe0, C4<1>, C4<1>;
+L_0x55f30e0ddc50 .functor AND 1, L_0x55f30e0de450, L_0x55f30e0de540, C4<1>, C4<1>;
+L_0x55f30e0e1870 .functor AND 1, L_0x55f30e0e1940, L_0x55f30e0de630, C4<1>, C4<1>;
+L_0x55f30e0e1a90 .functor AND 1, L_0x55f30e0e1b00, L_0x55f30e0e1c60, C4<1>, C4<1>;
+L_0x55f30e0e1d50 .functor AND 1, L_0x55f30e0e1e30, L_0x55f30e0e1ff0, C4<1>, C4<1>;
+L_0x55f30e0e2350 .functor AND 1, L_0x55f30e0e2410, L_0x55f30e0e2500, C4<1>, C4<1>;
+L_0x55f30e0e5c40 .functor AND 1, L_0x55f30e0e5d30, L_0x55f30e0e5dd0, C4<1>, C4<1>;
+L_0x55f30e0e1dc0 .functor AND 1, L_0x55f30e0e5f80, L_0x55f30e0e6070, C4<1>, C4<1>;
+L_0x55f30e0e6280 .functor AND 1, L_0x55f30e0e6380, L_0x55f30e0e6470, C4<1>, C4<1>;
+L_0x55f30e0e6940 .functor AND 1, L_0x55f30e0e6a00, L_0x55f30e0e6c30, C4<1>, C4<1>;
+L_0x7f5d71fc0210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0e9fe0 .functor OR 1, L_0x55f30e0ea0f0, L_0x7f5d71fc0210, C4<0>, C4<0>;
+L_0x7f5d71fc0258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0ea2f0 .functor OR 1, L_0x55f30e0ea360, L_0x7f5d71fc0258, C4<0>, C4<0>;
+L_0x7f5d71fc02a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0ea4a0 .functor OR 1, L_0x55f30e0ea050, L_0x7f5d71fc02a0, C4<0>, C4<0>;
+L_0x7f5d71fc02e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0ea7d0 .functor OR 1, L_0x55f30e0ea840, L_0x7f5d71fc02e8, C4<0>, C4<0>;
+L_0x7f5d71fc0330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0ea980 .functor OR 1, L_0x55f30e0eaab0, L_0x7f5d71fc0330, C4<0>, C4<0>;
+L_0x7f5d71fc0378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0eadb0 .functor OR 1, L_0x55f30e0eae20, L_0x7f5d71fc0378, C4<0>, C4<0>;
+L_0x7f5d71fc03c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+L_0x55f30e0eb460 .functor OR 1, L_0x55f30e0eb5f0, L_0x7f5d71fc03c0, C4<0>, C4<0>;
+v0x55f30e0d7700_0 .net "A", 3 0, v0x55f30e0dc920_0;  1 drivers
+v0x55f30e0d7800_0 .net "B", 3 0, v0x55f30e0dc9e0_0;  1 drivers
+v0x55f30e0d78e0_0 .net "S0", 4 0, L_0x55f30e0e1740;  1 drivers
+v0x55f30e0d79a0_0 .net "S1", 4 0, L_0x55f30e0e5a10;  1 drivers
+v0x55f30e0d7a80_0 .net "S2", 4 0, L_0x55f30e0e9eb0;  1 drivers
+v0x55f30e0d7bb0_0 .net "Y", 7 0, L_0x55f30e0eaf60;  alias, 1 drivers
+v0x55f30e0d7c90_0 .net *"_ivl_1", 0 0, L_0x55f30e0dcb20;  1 drivers
+v0x55f30e0d7d70_0 .net *"_ivl_10", 0 0, L_0x55f30e0dce80;  1 drivers
+v0x55f30e0d7e50_0 .net *"_ivl_101", 0 0, L_0x55f30e0e5dd0;  1 drivers
+v0x55f30e0d7f30_0 .net *"_ivl_102", 0 0, L_0x55f30e0e1dc0;  1 drivers
+v0x55f30e0d8010_0 .net *"_ivl_105", 0 0, L_0x55f30e0e5f80;  1 drivers
+v0x55f30e0d80f0_0 .net *"_ivl_107", 0 0, L_0x55f30e0e6070;  1 drivers
+v0x55f30e0d81d0_0 .net *"_ivl_108", 0 0, L_0x55f30e0e6280;  1 drivers
+v0x55f30e0d82b0_0 .net *"_ivl_111", 0 0, L_0x55f30e0e6380;  1 drivers
+v0x55f30e0d8390_0 .net *"_ivl_113", 0 0, L_0x55f30e0e6470;  1 drivers
+v0x55f30e0d8470_0 .net *"_ivl_114", 0 0, L_0x55f30e0e6940;  1 drivers
+v0x55f30e0d8550_0 .net *"_ivl_118", 0 0, L_0x55f30e0e6a00;  1 drivers
+v0x55f30e0d8740_0 .net *"_ivl_12", 0 0, L_0x55f30e0dcf70;  1 drivers
+v0x55f30e0d8820_0 .net *"_ivl_120", 0 0, L_0x55f30e0e6c30;  1 drivers
+v0x55f30e0d8900_0 .net *"_ivl_13", 0 0, L_0x55f30e0dd060;  1 drivers
+v0x55f30e0d89e0_0 .net *"_ivl_130", 0 0, L_0x55f30e0e9fe0;  1 drivers
+v0x55f30e0d8ac0_0 .net *"_ivl_133", 0 0, L_0x55f30e0ea0f0;  1 drivers
+v0x55f30e0d8ba0_0 .net/2u *"_ivl_134", 0 0, L_0x7f5d71fc0210;  1 drivers
+v0x55f30e0d8c80_0 .net *"_ivl_136", 0 0, L_0x55f30e0ea2f0;  1 drivers
+v0x55f30e0d8d60_0 .net *"_ivl_139", 0 0, L_0x55f30e0ea360;  1 drivers
+v0x55f30e0d8e40_0 .net/2u *"_ivl_140", 0 0, L_0x7f5d71fc0258;  1 drivers
+v0x55f30e0d8f20_0 .net *"_ivl_142", 0 0, L_0x55f30e0ea4a0;  1 drivers
+v0x55f30e0d9000_0 .net *"_ivl_145", 0 0, L_0x55f30e0ea050;  1 drivers
+v0x55f30e0d90e0_0 .net/2u *"_ivl_146", 0 0, L_0x7f5d71fc02a0;  1 drivers
+v0x55f30e0d91c0_0 .net *"_ivl_148", 0 0, L_0x55f30e0ea7d0;  1 drivers
+v0x55f30e0d92a0_0 .net *"_ivl_151", 0 0, L_0x55f30e0ea840;  1 drivers
+v0x55f30e0d9380_0 .net/2u *"_ivl_152", 0 0, L_0x7f5d71fc02e8;  1 drivers
+v0x55f30e0d9460_0 .net *"_ivl_154", 0 0, L_0x55f30e0ea980;  1 drivers
+v0x55f30e0d9750_0 .net *"_ivl_157", 0 0, L_0x55f30e0eaab0;  1 drivers
+v0x55f30e0d9830_0 .net/2u *"_ivl_158", 0 0, L_0x7f5d71fc0330;  1 drivers
+v0x55f30e0d9910_0 .net *"_ivl_16", 0 0, L_0x55f30e0dd0d0;  1 drivers
+v0x55f30e0d99f0_0 .net *"_ivl_160", 0 0, L_0x55f30e0eadb0;  1 drivers
+v0x55f30e0d9ad0_0 .net *"_ivl_163", 0 0, L_0x55f30e0eae20;  1 drivers
+v0x55f30e0d9bb0_0 .net/2u *"_ivl_164", 0 0, L_0x7f5d71fc0378;  1 drivers
+v0x55f30e0d9c90_0 .net *"_ivl_166", 0 0, L_0x55f30e0eb460;  1 drivers
+v0x55f30e0d9d70_0 .net *"_ivl_170", 0 0, L_0x55f30e0eb5f0;  1 drivers
+v0x55f30e0d9e50_0 .net/2u *"_ivl_171", 0 0, L_0x7f5d71fc03c0;  1 drivers
+v0x55f30e0d9f30_0 .net *"_ivl_18", 0 0, L_0x55f30e0dd1c0;  1 drivers
+v0x55f30e0da010_0 .net *"_ivl_19", 0 0, L_0x55f30e0dd330;  1 drivers
+v0x55f30e0da0f0_0 .net *"_ivl_22", 0 0, L_0x55f30e0dd3d0;  1 drivers
+v0x55f30e0da1d0_0 .net *"_ivl_24", 0 0, L_0x55f30e0dd470;  1 drivers
+v0x55f30e0da2b0_0 .net *"_ivl_25", 0 0, L_0x55f30e0dd740;  1 drivers
+v0x55f30e0da390_0 .net/2u *"_ivl_28", 0 0, L_0x7f5d71fc0018;  1 drivers
+v0x55f30e0da470_0 .net *"_ivl_30", 0 0, L_0x55f30e0dd850;  1 drivers
+v0x55f30e0da550_0 .net *"_ivl_33", 0 0, L_0x55f30e0dd900;  1 drivers
+v0x55f30e0da630_0 .net *"_ivl_35", 0 0, L_0x55f30e0dda50;  1 drivers
+v0x55f30e0da710_0 .net *"_ivl_36", 0 0, L_0x55f30e0ddaf0;  1 drivers
+v0x55f30e0da7f0_0 .net *"_ivl_39", 0 0, L_0x55f30e0ddb60;  1 drivers
+v0x55f30e0da8d0_0 .net *"_ivl_4", 0 0, L_0x55f30e0dcb90;  1 drivers
+v0x55f30e0da9b0_0 .net *"_ivl_41", 0 0, L_0x55f30e0ddcc0;  1 drivers
+v0x55f30e0daa90_0 .net *"_ivl_42", 0 0, L_0x55f30e0dddb0;  1 drivers
+v0x55f30e0dab70_0 .net *"_ivl_45", 0 0, L_0x55f30e0dde70;  1 drivers
+v0x55f30e0dac50_0 .net *"_ivl_47", 0 0, L_0x55f30e0ddfe0;  1 drivers
+v0x55f30e0dad30_0 .net *"_ivl_48", 0 0, L_0x55f30e0ddc50;  1 drivers
+v0x55f30e0dae10_0 .net *"_ivl_52", 0 0, L_0x55f30e0de450;  1 drivers
+v0x55f30e0daef0_0 .net *"_ivl_54", 0 0, L_0x55f30e0de540;  1 drivers
+v0x55f30e0dafd0_0 .net *"_ivl_6", 0 0, L_0x55f30e0dccd0;  1 drivers
+v0x55f30e0db0b0_0 .net *"_ivl_62", 0 0, L_0x55f30e0e1870;  1 drivers
+v0x55f30e0db190_0 .net *"_ivl_65", 0 0, L_0x55f30e0e1940;  1 drivers
+v0x55f30e0db270_0 .net *"_ivl_67", 0 0, L_0x55f30e0de630;  1 drivers
+v0x55f30e0db760_0 .net *"_ivl_68", 0 0, L_0x55f30e0e1a90;  1 drivers
+v0x55f30e0db840_0 .net *"_ivl_7", 0 0, L_0x55f30e0dce10;  1 drivers
+v0x55f30e0db920_0 .net *"_ivl_71", 0 0, L_0x55f30e0e1b00;  1 drivers
+v0x55f30e0dba00_0 .net *"_ivl_73", 0 0, L_0x55f30e0e1c60;  1 drivers
+v0x55f30e0dbae0_0 .net *"_ivl_74", 0 0, L_0x55f30e0e1d50;  1 drivers
+v0x55f30e0dbbc0_0 .net *"_ivl_77", 0 0, L_0x55f30e0e1e30;  1 drivers
+v0x55f30e0dbca0_0 .net *"_ivl_79", 0 0, L_0x55f30e0e1ff0;  1 drivers
+v0x55f30e0dbd80_0 .net *"_ivl_80", 0 0, L_0x55f30e0e2350;  1 drivers
+v0x55f30e0dbe60_0 .net *"_ivl_84", 0 0, L_0x55f30e0e2410;  1 drivers
+v0x55f30e0dbf40_0 .net *"_ivl_86", 0 0, L_0x55f30e0e2500;  1 drivers
+v0x55f30e0dc020_0 .net *"_ivl_96", 0 0, L_0x55f30e0e5c40;  1 drivers
+v0x55f30e0dc100_0 .net *"_ivl_99", 0 0, L_0x55f30e0e5d30;  1 drivers
+v0x55f30e0dc1e0_0 .net "a0", 3 0, L_0x55f30e0de1e0;  1 drivers
+v0x55f30e0dc2a0_0 .net "a1", 3 0, L_0x55f30e0e20e0;  1 drivers
+v0x55f30e0dc3b0_0 .net "a2", 3 0, L_0x55f30e0e6160;  1 drivers
+v0x55f30e0dc4c0_0 .net "b0", 3 0, L_0x55f30e0dd5b0;  1 drivers
+v0x55f30e0dc5d0_0 .net "overflow0", 0 0, L_0x55f30e0e1630;  1 drivers
+v0x55f30e0dc6c0_0 .net "overflow1", 0 0, L_0x55f30e0e56b0;  1 drivers
+v0x55f30e0dc7b0_0 .net "overflow2", 0 0, L_0x55f30e0e9b60;  1 drivers
+L_0x55f30e0dcb90 .part v0x55f30e0dc920_0, 0, 1;
+L_0x55f30e0dccd0 .part v0x55f30e0dc9e0_0, 0, 1;
+L_0x55f30e0dce80 .part v0x55f30e0dc920_0, 1, 1;
+L_0x55f30e0dcf70 .part v0x55f30e0dc9e0_0, 0, 1;
+L_0x55f30e0dd0d0 .part v0x55f30e0dc920_0, 2, 1;
+L_0x55f30e0dd1c0 .part v0x55f30e0dc9e0_0, 0, 1;
+L_0x55f30e0dd3d0 .part v0x55f30e0dc920_0, 3, 1;
+L_0x55f30e0dd470 .part v0x55f30e0dc9e0_0, 0, 1;
+L_0x55f30e0dd5b0 .concat8 [ 1 1 1 1], L_0x55f30e0dce10, L_0x55f30e0dd060, L_0x55f30e0dd330, L_0x55f30e0dd740;
+L_0x55f30e0dd900 .part v0x55f30e0dc920_0, 0, 1;
+L_0x55f30e0dda50 .part v0x55f30e0dc9e0_0, 1, 1;
+L_0x55f30e0ddb60 .part v0x55f30e0dc920_0, 1, 1;
+L_0x55f30e0ddcc0 .part v0x55f30e0dc9e0_0, 1, 1;
+L_0x55f30e0dde70 .part v0x55f30e0dc920_0, 2, 1;
+L_0x55f30e0ddfe0 .part v0x55f30e0dc9e0_0, 1, 1;
+L_0x55f30e0de1e0 .concat8 [ 1 1 1 1], L_0x55f30e0dd850, L_0x55f30e0ddaf0, L_0x55f30e0dddb0, L_0x55f30e0ddc50;
+L_0x55f30e0de450 .part v0x55f30e0dc920_0, 3, 1;
+L_0x55f30e0de540 .part v0x55f30e0dc9e0_0, 1, 1;
+L_0x55f30e0e1740 .concat8 [ 4 1 0 0], L_0x55f30e0e03e0, L_0x55f30e0dff40;
+L_0x55f30e0e1940 .part v0x55f30e0dc920_0, 0, 1;
+L_0x55f30e0de630 .part v0x55f30e0dc9e0_0, 2, 1;
+L_0x55f30e0e1b00 .part v0x55f30e0dc920_0, 1, 1;
+L_0x55f30e0e1c60 .part v0x55f30e0dc9e0_0, 2, 1;
+L_0x55f30e0e1e30 .part v0x55f30e0dc920_0, 2, 1;
+L_0x55f30e0e1ff0 .part v0x55f30e0dc9e0_0, 2, 1;
+L_0x55f30e0e20e0 .concat8 [ 1 1 1 1], L_0x55f30e0e1870, L_0x55f30e0e1a90, L_0x55f30e0e1d50, L_0x55f30e0e2350;
+L_0x55f30e0e2410 .part v0x55f30e0dc920_0, 3, 1;
+L_0x55f30e0e2500 .part v0x55f30e0dc9e0_0, 2, 1;
+L_0x55f30e0e57c0 .part L_0x55f30e0e1740, 1, 4;
+L_0x55f30e0e5a10 .concat8 [ 4 1 0 0], L_0x55f30e0e45b0, L_0x55f30e0e4110;
+L_0x55f30e0e5d30 .part v0x55f30e0dc920_0, 0, 1;
+L_0x55f30e0e5dd0 .part v0x55f30e0dc9e0_0, 3, 1;
+L_0x55f30e0e5f80 .part v0x55f30e0dc920_0, 1, 1;
+L_0x55f30e0e6070 .part v0x55f30e0dc9e0_0, 3, 1;
+L_0x55f30e0e6380 .part v0x55f30e0dc920_0, 2, 1;
+L_0x55f30e0e6470 .part v0x55f30e0dc9e0_0, 3, 1;
+L_0x55f30e0e6160 .concat8 [ 1 1 1 1], L_0x55f30e0e5c40, L_0x55f30e0e1dc0, L_0x55f30e0e6280, L_0x55f30e0e6940;
+L_0x55f30e0e6a00 .part v0x55f30e0dc920_0, 3, 1;
+L_0x55f30e0e6c30 .part v0x55f30e0dc9e0_0, 3, 1;
+L_0x55f30e0e9c70 .part L_0x55f30e0e5a10, 1, 4;
+L_0x55f30e0e9eb0 .concat8 [ 4 1 0 0], L_0x55f30e0e8bb0, L_0x55f30e0e8710;
+L_0x55f30e0ea0f0 .part L_0x55f30e0e1740, 0, 1;
+L_0x55f30e0ea360 .part L_0x55f30e0e5a10, 0, 1;
+L_0x55f30e0ea050 .part L_0x55f30e0e9eb0, 0, 1;
+L_0x55f30e0ea840 .part L_0x55f30e0e9eb0, 1, 1;
+L_0x55f30e0eaab0 .part L_0x55f30e0e9eb0, 2, 1;
+L_0x55f30e0eae20 .part L_0x55f30e0e9eb0, 3, 1;
+LS_0x55f30e0eaf60_0_0 .concat8 [ 1 1 1 1], L_0x55f30e0dcb20, L_0x55f30e0e9fe0, L_0x55f30e0ea2f0, L_0x55f30e0ea4a0;
+LS_0x55f30e0eaf60_0_4 .concat8 [ 1 1 1 1], L_0x55f30e0ea7d0, L_0x55f30e0ea980, L_0x55f30e0eadb0, L_0x55f30e0eb460;
+L_0x55f30e0eaf60 .concat8 [ 4 4 0 0], LS_0x55f30e0eaf60_0_0, LS_0x55f30e0eaf60_0_4;
+L_0x55f30e0eb5f0 .part L_0x55f30e0e9eb0, 4, 1;
+S_0x55f30e094c90 .scope module, "add0" "addition" 3 26, 4 1 0, S_0x55f30e070c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /INPUT 1 "CarryIN";
+    .port_info 3 /OUTPUT 4 "Y";
+    .port_info 4 /OUTPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflow";
+v0x55f30e0c81a0_0 .net "A", 3 0, L_0x55f30e0de1e0;  alias, 1 drivers
+v0x55f30e0c8280_0 .net "B", 3 0, L_0x55f30e0dd5b0;  alias, 1 drivers
+v0x55f30e0c8350_0 .net "Carry4", 3 0, L_0x55f30e0eb730;  1 drivers
+L_0x7f5d71fc00a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x55f30e0c8420_0 .net "CarryIN", 0 0, L_0x7f5d71fc00a8;  1 drivers
+v0x55f30e0c84c0_0 .net "CarryOUT", 0 0, L_0x55f30e0dff40;  1 drivers
+v0x55f30e0c8600_0 .net "Y", 3 0, L_0x55f30e0e03e0;  1 drivers
+o0x7f5d7200a578 .functor BUFZ 1, C4<z>; HiZ drive
+; Elide local net with no drivers, v0x55f30e0c86c0_0 name=_ivl_41
+v0x55f30e0c8780_0 .net "overflow", 0 0, L_0x55f30e0e1630;  alias, 1 drivers
+L_0x55f30e0dea40 .part L_0x55f30e0de1e0, 0, 1;
+L_0x55f30e0deb70 .part L_0x55f30e0dd5b0, 0, 1;
+L_0x55f30e0deff0 .part L_0x55f30e0de1e0, 1, 1;
+L_0x55f30e0df120 .part L_0x55f30e0dd5b0, 1, 1;
+L_0x55f30e0df250 .part L_0x55f30e0eb730, 0, 1;
+L_0x55f30e0df720 .part L_0x55f30e0de1e0, 2, 1;
+L_0x55f30e0df890 .part L_0x55f30e0dd5b0, 2, 1;
+L_0x55f30e0df9c0 .part L_0x55f30e0eb730, 1, 1;
+L_0x55f30e0dfff0 .part L_0x55f30e0de1e0, 3, 1;
+L_0x55f30e0e0120 .part L_0x55f30e0dd5b0, 3, 1;
+L_0x55f30e0e02b0 .part L_0x55f30e0eb730, 2, 1;
+L_0x55f30e0e03e0 .concat8 [ 1 1 1 1], L_0x55f30e0de960, L_0x55f30e0def10, L_0x55f30e0df5b0, L_0x55f30e0dfe60;
+L_0x55f30e0eb730 .concat [ 1 1 1 1], L_0x55f30e0de9d0, L_0x55f30e0def80, L_0x55f30e0df690, o0x7f5d7200a578;
+S_0x55f30e087a30 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x55f30e094c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0de9d0 .functor OR 1, L_0x55f30e0de6d0, L_0x55f30e0de8a0, C4<0>, C4<0>;
+v0x55f30e0c26d0_0 .net "A", 0 0, L_0x55f30e0dea40;  1 drivers
+v0x55f30e0c2790_0 .net "B", 0 0, L_0x55f30e0deb70;  1 drivers
+v0x55f30e0c2860_0 .net "Carry", 0 0, L_0x7f5d71fc00a8;  alias, 1 drivers
+v0x55f30e0c2960_0 .net "CarryO", 0 0, L_0x55f30e0de9d0;  1 drivers
+v0x55f30e0c2a00_0 .net "Sum", 0 0, L_0x55f30e0de960;  1 drivers
+v0x55f30e0c2aa0_0 .net "and1", 0 0, L_0x55f30e0de6d0;  1 drivers
+v0x55f30e0c2b70_0 .net "and2", 0 0, L_0x55f30e0de8a0;  1 drivers
+v0x55f30e0c2c40_0 .net "xor1", 0 0, L_0x55f30e0de830;  1 drivers
+S_0x55f30e0a2230 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e087a30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0de6d0 .functor AND 1, L_0x55f30e0dea40, L_0x55f30e0deb70, C4<1>, C4<1>;
+L_0x55f30e0de830 .functor XOR 1, L_0x55f30e0dea40, L_0x55f30e0deb70, C4<0>, C4<0>;
+v0x55f30e0902b0_0 .net "A", 0 0, L_0x55f30e0dea40;  alias, 1 drivers
+v0x55f30e084b20_0 .net "B", 0 0, L_0x55f30e0deb70;  alias, 1 drivers
+v0x55f30e083050_0 .net "Carry", 0 0, L_0x55f30e0de6d0;  alias, 1 drivers
+v0x55f30e0a7570_0 .net "Sum", 0 0, L_0x55f30e0de830;  alias, 1 drivers
+S_0x55f30e0c22e0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e087a30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0de8a0 .functor AND 1, L_0x55f30e0de830, L_0x7f5d71fc00a8, C4<1>, C4<1>;
+L_0x55f30e0de960 .functor XOR 1, L_0x55f30e0de830, L_0x7f5d71fc00a8, C4<0>, C4<0>;
+v0x55f30e0a6830_0 .net "A", 0 0, L_0x55f30e0de830;  alias, 1 drivers
+v0x55f30e0127f0_0 .net "B", 0 0, L_0x7f5d71fc00a8;  alias, 1 drivers
+v0x55f30e0c2490_0 .net "Carry", 0 0, L_0x55f30e0de8a0;  alias, 1 drivers
+v0x55f30e0c2560_0 .net "Sum", 0 0, L_0x55f30e0de960;  alias, 1 drivers
+S_0x55f30e0c2d30 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x55f30e094c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0def80 .functor OR 1, L_0x55f30e0ded30, L_0x55f30e0dee10, C4<0>, C4<0>;
+v0x55f30e0c3ab0_0 .net "A", 0 0, L_0x55f30e0deff0;  1 drivers
+v0x55f30e0c3b70_0 .net "B", 0 0, L_0x55f30e0df120;  1 drivers
+v0x55f30e0c3c40_0 .net "Carry", 0 0, L_0x55f30e0df250;  1 drivers
+v0x55f30e0c3d40_0 .net "CarryO", 0 0, L_0x55f30e0def80;  1 drivers
+v0x55f30e0c3de0_0 .net "Sum", 0 0, L_0x55f30e0def10;  1 drivers
+v0x55f30e0c3ed0_0 .net "and1", 0 0, L_0x55f30e0ded30;  1 drivers
+v0x55f30e0c3fa0_0 .net "and2", 0 0, L_0x55f30e0dee10;  1 drivers
+v0x55f30e0c4070_0 .net "xor1", 0 0, L_0x55f30e0deda0;  1 drivers
+S_0x55f30e0c2f10 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c2d30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0ded30 .functor AND 1, L_0x55f30e0deff0, L_0x55f30e0df120, C4<1>, C4<1>;
+L_0x55f30e0deda0 .functor XOR 1, L_0x55f30e0deff0, L_0x55f30e0df120, C4<0>, C4<0>;
+v0x55f30e0c3120_0 .net "A", 0 0, L_0x55f30e0deff0;  alias, 1 drivers
+v0x55f30e0c3200_0 .net "B", 0 0, L_0x55f30e0df120;  alias, 1 drivers
+v0x55f30e0c32c0_0 .net "Carry", 0 0, L_0x55f30e0ded30;  alias, 1 drivers
+v0x55f30e0c3390_0 .net "Sum", 0 0, L_0x55f30e0deda0;  alias, 1 drivers
+S_0x55f30e0c3500 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c2d30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0dee10 .functor AND 1, L_0x55f30e0deda0, L_0x55f30e0df250, C4<1>, C4<1>;
+L_0x55f30e0def10 .functor XOR 1, L_0x55f30e0deda0, L_0x55f30e0df250, C4<0>, C4<0>;
+v0x55f30e0c3700_0 .net "A", 0 0, L_0x55f30e0deda0;  alias, 1 drivers
+v0x55f30e0c37d0_0 .net "B", 0 0, L_0x55f30e0df250;  alias, 1 drivers
+v0x55f30e0c3870_0 .net "Carry", 0 0, L_0x55f30e0dee10;  alias, 1 drivers
+v0x55f30e0c3940_0 .net "Sum", 0 0, L_0x55f30e0def10;  alias, 1 drivers
+S_0x55f30e0c4160 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x55f30e094c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0df690 .functor OR 1, L_0x55f30e0df380, L_0x55f30e0df460, C4<0>, C4<0>;
+v0x55f30e0c4ef0_0 .net "A", 0 0, L_0x55f30e0df720;  1 drivers
+v0x55f30e0c4fb0_0 .net "B", 0 0, L_0x55f30e0df890;  1 drivers
+v0x55f30e0c5080_0 .net "Carry", 0 0, L_0x55f30e0df9c0;  1 drivers
+v0x55f30e0c5180_0 .net "CarryO", 0 0, L_0x55f30e0df690;  1 drivers
+v0x55f30e0c5220_0 .net "Sum", 0 0, L_0x55f30e0df5b0;  1 drivers
+v0x55f30e0c5310_0 .net "and1", 0 0, L_0x55f30e0df380;  1 drivers
+v0x55f30e0c53e0_0 .net "and2", 0 0, L_0x55f30e0df460;  1 drivers
+v0x55f30e0c54b0_0 .net "xor1", 0 0, L_0x55f30e0df3f0;  1 drivers
+S_0x55f30e0c4370 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c4160;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0df380 .functor AND 1, L_0x55f30e0df720, L_0x55f30e0df890, C4<1>, C4<1>;
+L_0x55f30e0df3f0 .functor XOR 1, L_0x55f30e0df720, L_0x55f30e0df890, C4<0>, C4<0>;
+v0x55f30e0c4580_0 .net "A", 0 0, L_0x55f30e0df720;  alias, 1 drivers
+v0x55f30e0c4640_0 .net "B", 0 0, L_0x55f30e0df890;  alias, 1 drivers
+v0x55f30e0c4700_0 .net "Carry", 0 0, L_0x55f30e0df380;  alias, 1 drivers
+v0x55f30e0c47d0_0 .net "Sum", 0 0, L_0x55f30e0df3f0;  alias, 1 drivers
+S_0x55f30e0c4940 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c4160;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0df460 .functor AND 1, L_0x55f30e0df3f0, L_0x55f30e0df9c0, C4<1>, C4<1>;
+L_0x55f30e0df5b0 .functor XOR 1, L_0x55f30e0df3f0, L_0x55f30e0df9c0, C4<0>, C4<0>;
+v0x55f30e0c4b40_0 .net "A", 0 0, L_0x55f30e0df3f0;  alias, 1 drivers
+v0x55f30e0c4c10_0 .net "B", 0 0, L_0x55f30e0df9c0;  alias, 1 drivers
+v0x55f30e0c4cb0_0 .net "Carry", 0 0, L_0x55f30e0df460;  alias, 1 drivers
+v0x55f30e0c4d80_0 .net "Sum", 0 0, L_0x55f30e0df5b0;  alias, 1 drivers
+S_0x55f30e0c55a0 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x55f30e094c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0dff40 .functor OR 1, L_0x55f30e0dfb40, L_0x55f30e0dfcd0, C4<0>, C4<0>;
+v0x55f30e0c6320_0 .net "A", 0 0, L_0x55f30e0dfff0;  1 drivers
+v0x55f30e0c63e0_0 .net "B", 0 0, L_0x55f30e0e0120;  1 drivers
+v0x55f30e0c64b0_0 .net "Carry", 0 0, L_0x55f30e0e02b0;  1 drivers
+v0x55f30e0c65b0_0 .net "CarryO", 0 0, L_0x55f30e0dff40;  alias, 1 drivers
+v0x55f30e0c6650_0 .net "Sum", 0 0, L_0x55f30e0dfe60;  1 drivers
+v0x55f30e0c6740_0 .net "and1", 0 0, L_0x55f30e0dfb40;  1 drivers
+v0x55f30e0c6810_0 .net "and2", 0 0, L_0x55f30e0dfcd0;  1 drivers
+v0x55f30e0c68e0_0 .net "xor1", 0 0, L_0x55f30e0dfc40;  1 drivers
+S_0x55f30e0c5780 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c55a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0dfb40 .functor AND 1, L_0x55f30e0dfff0, L_0x55f30e0e0120, C4<1>, C4<1>;
+L_0x55f30e0dfc40 .functor XOR 1, L_0x55f30e0dfff0, L_0x55f30e0e0120, C4<0>, C4<0>;
+v0x55f30e0c5990_0 .net "A", 0 0, L_0x55f30e0dfff0;  alias, 1 drivers
+v0x55f30e0c5a70_0 .net "B", 0 0, L_0x55f30e0e0120;  alias, 1 drivers
+v0x55f30e0c5b30_0 .net "Carry", 0 0, L_0x55f30e0dfb40;  alias, 1 drivers
+v0x55f30e0c5c00_0 .net "Sum", 0 0, L_0x55f30e0dfc40;  alias, 1 drivers
+S_0x55f30e0c5d70 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c55a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0dfcd0 .functor AND 1, L_0x55f30e0dfc40, L_0x55f30e0e02b0, C4<1>, C4<1>;
+L_0x55f30e0dfe60 .functor XOR 1, L_0x55f30e0dfc40, L_0x55f30e0e02b0, C4<0>, C4<0>;
+v0x55f30e0c5f70_0 .net "A", 0 0, L_0x55f30e0dfc40;  alias, 1 drivers
+v0x55f30e0c6040_0 .net "B", 0 0, L_0x55f30e0e02b0;  alias, 1 drivers
+v0x55f30e0c60e0_0 .net "Carry", 0 0, L_0x55f30e0dfcd0;  alias, 1 drivers
+v0x55f30e0c61b0_0 .net "Sum", 0 0, L_0x55f30e0dfe60;  alias, 1 drivers
+S_0x55f30e0c69d0 .scope module, "od1" "overflowDetect" 4 17, 7 1 0, S_0x55f30e094c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 2 "opCode";
+    .port_info 1 /INPUT 4 "A";
+    .port_info 2 /INPUT 4 "B";
+    .port_info 3 /INPUT 4 "Y";
+    .port_info 4 /INPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflowDetect";
+L_0x55f30e0e04f0 .functor OR 1, L_0x55f30e0e0580, L_0x55f30e0e0620, C4<0>, C4<0>;
+L_0x55f30e0e06c0 .functor XNOR 1, L_0x55f30e0e0730, L_0x55f30e0e0930, C4<0>, C4<0>;
+L_0x55f30e0e0b30 .functor XOR 1, L_0x55f30e0e0ba0, L_0x55f30e0e0c90, C4<0>, C4<0>;
+L_0x55f30e0e0dc0 .functor XOR 1, L_0x55f30e0e0e30, L_0x55f30e0e0f20, C4<0>, C4<0>;
+L_0x55f30e0e1060 .functor AND 1, L_0x55f30e0e06c0, L_0x55f30e0e1120, C4<1>, C4<1>;
+L_0x55f30e0e1210 .functor AND 1, L_0x55f30e0e0b30, L_0x55f30e0e1310, C4<1>, C4<1>;
+L_0x55f30e0e1460 .functor OR 1, L_0x55f30e0e1060, L_0x55f30e0e1210, C4<0>, C4<0>;
+L_0x55f30e0e14d0 .functor AND 1, L_0x55f30e0e1460, L_0x55f30e0e0dc0, C4<1>, C4<1>;
+L_0x55f30e0e1630 .functor AND 1, L_0x55f30e0e04f0, L_0x55f30e0e14d0, C4<1>, C4<1>;
+v0x55f30e0c6ca0_0 .net "A", 3 0, L_0x55f30e0de1e0;  alias, 1 drivers
+v0x55f30e0c6d80_0 .net "B", 3 0, L_0x55f30e0dd5b0;  alias, 1 drivers
+v0x55f30e0c6e60_0 .net "CarryOUT", 0 0, L_0x55f30e0dff40;  alias, 1 drivers
+v0x55f30e0c6f00_0 .net "Y", 3 0, L_0x55f30e0e03e0;  alias, 1 drivers
+v0x55f30e0c6fa0_0 .net *"_ivl_1", 0 0, L_0x55f30e0e0580;  1 drivers
+v0x55f30e0c70d0_0 .net *"_ivl_11", 0 0, L_0x55f30e0e0c90;  1 drivers
+v0x55f30e0c71b0_0 .net *"_ivl_13", 0 0, L_0x55f30e0e0e30;  1 drivers
+v0x55f30e0c7290_0 .net *"_ivl_15", 0 0, L_0x55f30e0e0f20;  1 drivers
+v0x55f30e0c7370_0 .net *"_ivl_17", 0 0, L_0x55f30e0e1120;  1 drivers
+v0x55f30e0c74e0_0 .net *"_ivl_19", 0 0, L_0x55f30e0e1310;  1 drivers
+v0x55f30e0c75c0_0 .net *"_ivl_3", 0 0, L_0x55f30e0e0620;  1 drivers
+v0x55f30e0c76a0_0 .net *"_ivl_5", 0 0, L_0x55f30e0e0730;  1 drivers
+v0x55f30e0c7780_0 .net *"_ivl_7", 0 0, L_0x55f30e0e0930;  1 drivers
+v0x55f30e0c7860_0 .net *"_ivl_9", 0 0, L_0x55f30e0e0ba0;  1 drivers
+v0x55f30e0c7940_0 .net "addOverflow", 0 0, L_0x55f30e0e1060;  1 drivers
+v0x55f30e0c7a00_0 .net "detect1", 0 0, L_0x55f30e0e1460;  1 drivers
+v0x55f30e0c7ac0_0 .net "detect2", 0 0, L_0x55f30e0e14d0;  1 drivers
+v0x55f30e0c7b80_0 .net "opC", 0 0, L_0x55f30e0e04f0;  1 drivers
+L_0x7f5d71fc0060 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x55f30e0c7c40_0 .net "opCode", 1 0, L_0x7f5d71fc0060;  1 drivers
+v0x55f30e0c7d20_0 .net "overflowDetect", 0 0, L_0x55f30e0e1630;  alias, 1 drivers
+v0x55f30e0c7de0_0 .net "sign1", 0 0, L_0x55f30e0e06c0;  1 drivers
+v0x55f30e0c7ea0_0 .net "sign2", 0 0, L_0x55f30e0e0dc0;  1 drivers
+v0x55f30e0c7f60_0 .net "sign3", 0 0, L_0x55f30e0e0b30;  1 drivers
+v0x55f30e0c8020_0 .net "subOverflow", 0 0, L_0x55f30e0e1210;  1 drivers
+L_0x55f30e0e0580 .part L_0x7f5d71fc0060, 0, 1;
+L_0x55f30e0e0620 .part L_0x7f5d71fc0060, 1, 1;
+L_0x55f30e0e0730 .part L_0x55f30e0de1e0, 3, 1;
+L_0x55f30e0e0930 .part L_0x55f30e0dd5b0, 3, 1;
+L_0x55f30e0e0ba0 .part L_0x55f30e0de1e0, 3, 1;
+L_0x55f30e0e0c90 .part L_0x55f30e0dd5b0, 3, 1;
+L_0x55f30e0e0e30 .part L_0x55f30e0e03e0, 3, 1;
+L_0x55f30e0e0f20 .part L_0x55f30e0de1e0, 3, 1;
+L_0x55f30e0e1120 .part L_0x7f5d71fc0060, 0, 1;
+L_0x55f30e0e1310 .part L_0x7f5d71fc0060, 1, 1;
+S_0x55f30e0c88c0 .scope module, "add1" "addition" 3 42, 4 1 0, S_0x55f30e070c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /INPUT 1 "CarryIN";
+    .port_info 3 /OUTPUT 4 "Y";
+    .port_info 4 /OUTPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflow";
+v0x55f30e0cf710_0 .net "A", 3 0, L_0x55f30e0e20e0;  alias, 1 drivers
+v0x55f30e0cf7f0_0 .net "B", 3 0, L_0x55f30e0e57c0;  1 drivers
+v0x55f30e0cf8c0_0 .net "Carry4", 3 0, L_0x55f30e0eb900;  1 drivers
+L_0x7f5d71fc0138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x55f30e0cf990_0 .net "CarryIN", 0 0, L_0x7f5d71fc0138;  1 drivers
+v0x55f30e0cfa30_0 .net "CarryOUT", 0 0, L_0x55f30e0e4110;  1 drivers
+v0x55f30e0cfb70_0 .net "Y", 3 0, L_0x55f30e0e45b0;  1 drivers
+o0x7f5d7200bc28 .functor BUFZ 1, C4<z>; HiZ drive
+; Elide local net with no drivers, v0x55f30e0cfc30_0 name=_ivl_41
+v0x55f30e0cfcf0_0 .net "overflow", 0 0, L_0x55f30e0e56b0;  alias, 1 drivers
+L_0x55f30e0e2b70 .part L_0x55f30e0e20e0, 0, 1;
+L_0x55f30e0e2d30 .part L_0x55f30e0e57c0, 0, 1;
+L_0x55f30e0e31c0 .part L_0x55f30e0e20e0, 1, 1;
+L_0x55f30e0e32f0 .part L_0x55f30e0e57c0, 1, 1;
+L_0x55f30e0e3420 .part L_0x55f30e0eb900, 0, 1;
+L_0x55f30e0e38b0 .part L_0x55f30e0e20e0, 2, 1;
+L_0x55f30e0e3a20 .part L_0x55f30e0e57c0, 2, 1;
+L_0x55f30e0e3be0 .part L_0x55f30e0eb900, 1, 1;
+L_0x55f30e0e41c0 .part L_0x55f30e0e20e0, 3, 1;
+L_0x55f30e0e42f0 .part L_0x55f30e0e57c0, 3, 1;
+L_0x55f30e0e4480 .part L_0x55f30e0eb900, 2, 1;
+L_0x55f30e0e45b0 .concat8 [ 1 1 1 1], L_0x55f30e0e2a00, L_0x55f30e0e3090, L_0x55f30e0e3780, L_0x55f30e0e4030;
+L_0x55f30e0eb900 .concat [ 1 1 1 1], L_0x55f30e0e2b00, L_0x55f30e0e3150, L_0x55f30e0e3840, o0x7f5d7200bc28;
+S_0x55f30e0c8b60 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x55f30e0c88c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e2b00 .functor OR 1, L_0x55f30e0e26e0, L_0x55f30e0e28b0, C4<0>, C4<0>;
+v0x55f30e0c99e0_0 .net "A", 0 0, L_0x55f30e0e2b70;  1 drivers
+v0x55f30e0c9aa0_0 .net "B", 0 0, L_0x55f30e0e2d30;  1 drivers
+v0x55f30e0c9b70_0 .net "Carry", 0 0, L_0x7f5d71fc0138;  alias, 1 drivers
+v0x55f30e0c9c70_0 .net "CarryO", 0 0, L_0x55f30e0e2b00;  1 drivers
+v0x55f30e0c9d10_0 .net "Sum", 0 0, L_0x55f30e0e2a00;  1 drivers
+v0x55f30e0c9e00_0 .net "and1", 0 0, L_0x55f30e0e26e0;  1 drivers
+v0x55f30e0c9ed0_0 .net "and2", 0 0, L_0x55f30e0e28b0;  1 drivers
+v0x55f30e0c9fa0_0 .net "xor1", 0 0, L_0x55f30e0e2840;  1 drivers
+S_0x55f30e0c8d40 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c8b60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e26e0 .functor AND 1, L_0x55f30e0e2b70, L_0x55f30e0e2d30, C4<1>, C4<1>;
+L_0x55f30e0e2840 .functor XOR 1, L_0x55f30e0e2b70, L_0x55f30e0e2d30, C4<0>, C4<0>;
+v0x55f30e0c8fe0_0 .net "A", 0 0, L_0x55f30e0e2b70;  alias, 1 drivers
+v0x55f30e0c90c0_0 .net "B", 0 0, L_0x55f30e0e2d30;  alias, 1 drivers
+v0x55f30e0c9180_0 .net "Carry", 0 0, L_0x55f30e0e26e0;  alias, 1 drivers
+v0x55f30e0c9250_0 .net "Sum", 0 0, L_0x55f30e0e2840;  alias, 1 drivers
+S_0x55f30e0c93c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c8b60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e28b0 .functor AND 1, L_0x55f30e0e2840, L_0x7f5d71fc0138, C4<1>, C4<1>;
+L_0x55f30e0e2a00 .functor XOR 1, L_0x55f30e0e2840, L_0x7f5d71fc0138, C4<0>, C4<0>;
+v0x55f30e0c9630_0 .net "A", 0 0, L_0x55f30e0e2840;  alias, 1 drivers
+v0x55f30e0c9700_0 .net "B", 0 0, L_0x7f5d71fc0138;  alias, 1 drivers
+v0x55f30e0c97a0_0 .net "Carry", 0 0, L_0x55f30e0e28b0;  alias, 1 drivers
+v0x55f30e0c9870_0 .net "Sum", 0 0, L_0x55f30e0e2a00;  alias, 1 drivers
+S_0x55f30e0ca090 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x55f30e0c88c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e3150 .functor OR 1, L_0x55f30e0e2e60, L_0x55f30e0e2f40, C4<0>, C4<0>;
+v0x55f30e0caef0_0 .net "A", 0 0, L_0x55f30e0e31c0;  1 drivers
+v0x55f30e0cafb0_0 .net "B", 0 0, L_0x55f30e0e32f0;  1 drivers
+v0x55f30e0cb080_0 .net "Carry", 0 0, L_0x55f30e0e3420;  1 drivers
+v0x55f30e0cb180_0 .net "CarryO", 0 0, L_0x55f30e0e3150;  1 drivers
+v0x55f30e0cb220_0 .net "Sum", 0 0, L_0x55f30e0e3090;  1 drivers
+v0x55f30e0cb310_0 .net "and1", 0 0, L_0x55f30e0e2e60;  1 drivers
+v0x55f30e0cb3e0_0 .net "and2", 0 0, L_0x55f30e0e2f40;  1 drivers
+v0x55f30e0cb4b0_0 .net "xor1", 0 0, L_0x55f30e0e2ed0;  1 drivers
+S_0x55f30e0ca270 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0ca090;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e2e60 .functor AND 1, L_0x55f30e0e31c0, L_0x55f30e0e32f0, C4<1>, C4<1>;
+L_0x55f30e0e2ed0 .functor XOR 1, L_0x55f30e0e31c0, L_0x55f30e0e32f0, C4<0>, C4<0>;
+v0x55f30e0ca4f0_0 .net "A", 0 0, L_0x55f30e0e31c0;  alias, 1 drivers
+v0x55f30e0ca5d0_0 .net "B", 0 0, L_0x55f30e0e32f0;  alias, 1 drivers
+v0x55f30e0ca690_0 .net "Carry", 0 0, L_0x55f30e0e2e60;  alias, 1 drivers
+v0x55f30e0ca760_0 .net "Sum", 0 0, L_0x55f30e0e2ed0;  alias, 1 drivers
+S_0x55f30e0ca8d0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0ca090;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e2f40 .functor AND 1, L_0x55f30e0e2ed0, L_0x55f30e0e3420, C4<1>, C4<1>;
+L_0x55f30e0e3090 .functor XOR 1, L_0x55f30e0e2ed0, L_0x55f30e0e3420, C4<0>, C4<0>;
+v0x55f30e0cab40_0 .net "A", 0 0, L_0x55f30e0e2ed0;  alias, 1 drivers
+v0x55f30e0cac10_0 .net "B", 0 0, L_0x55f30e0e3420;  alias, 1 drivers
+v0x55f30e0cacb0_0 .net "Carry", 0 0, L_0x55f30e0e2f40;  alias, 1 drivers
+v0x55f30e0cad80_0 .net "Sum", 0 0, L_0x55f30e0e3090;  alias, 1 drivers
+S_0x55f30e0cb5a0 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x55f30e0c88c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e3840 .functor OR 1, L_0x55f30e0e3550, L_0x55f30e0e3630, C4<0>, C4<0>;
+v0x55f30e0cc410_0 .net "A", 0 0, L_0x55f30e0e38b0;  1 drivers
+v0x55f30e0cc4d0_0 .net "B", 0 0, L_0x55f30e0e3a20;  1 drivers
+v0x55f30e0cc5a0_0 .net "Carry", 0 0, L_0x55f30e0e3be0;  1 drivers
+v0x55f30e0cc6a0_0 .net "CarryO", 0 0, L_0x55f30e0e3840;  1 drivers
+v0x55f30e0cc740_0 .net "Sum", 0 0, L_0x55f30e0e3780;  1 drivers
+v0x55f30e0cc830_0 .net "and1", 0 0, L_0x55f30e0e3550;  1 drivers
+v0x55f30e0cc900_0 .net "and2", 0 0, L_0x55f30e0e3630;  1 drivers
+v0x55f30e0cc9d0_0 .net "xor1", 0 0, L_0x55f30e0e35c0;  1 drivers
+S_0x55f30e0cb7b0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0cb5a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e3550 .functor AND 1, L_0x55f30e0e38b0, L_0x55f30e0e3a20, C4<1>, C4<1>;
+L_0x55f30e0e35c0 .functor XOR 1, L_0x55f30e0e38b0, L_0x55f30e0e3a20, C4<0>, C4<0>;
+v0x55f30e0cba30_0 .net "A", 0 0, L_0x55f30e0e38b0;  alias, 1 drivers
+v0x55f30e0cbaf0_0 .net "B", 0 0, L_0x55f30e0e3a20;  alias, 1 drivers
+v0x55f30e0cbbb0_0 .net "Carry", 0 0, L_0x55f30e0e3550;  alias, 1 drivers
+v0x55f30e0cbc80_0 .net "Sum", 0 0, L_0x55f30e0e35c0;  alias, 1 drivers
+S_0x55f30e0cbdf0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0cb5a0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e3630 .functor AND 1, L_0x55f30e0e35c0, L_0x55f30e0e3be0, C4<1>, C4<1>;
+L_0x55f30e0e3780 .functor XOR 1, L_0x55f30e0e35c0, L_0x55f30e0e3be0, C4<0>, C4<0>;
+v0x55f30e0cc060_0 .net "A", 0 0, L_0x55f30e0e35c0;  alias, 1 drivers
+v0x55f30e0cc130_0 .net "B", 0 0, L_0x55f30e0e3be0;  alias, 1 drivers
+v0x55f30e0cc1d0_0 .net "Carry", 0 0, L_0x55f30e0e3630;  alias, 1 drivers
+v0x55f30e0cc2a0_0 .net "Sum", 0 0, L_0x55f30e0e3780;  alias, 1 drivers
+S_0x55f30e0ccac0 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x55f30e0c88c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e4110 .functor OR 1, L_0x55f30e0e3d60, L_0x55f30e0e3ea0, C4<0>, C4<0>;
+v0x55f30e0cd920_0 .net "A", 0 0, L_0x55f30e0e41c0;  1 drivers
+v0x55f30e0cd9e0_0 .net "B", 0 0, L_0x55f30e0e42f0;  1 drivers
+v0x55f30e0cdab0_0 .net "Carry", 0 0, L_0x55f30e0e4480;  1 drivers
+v0x55f30e0cdbb0_0 .net "CarryO", 0 0, L_0x55f30e0e4110;  alias, 1 drivers
+v0x55f30e0cdc50_0 .net "Sum", 0 0, L_0x55f30e0e4030;  1 drivers
+v0x55f30e0cdd40_0 .net "and1", 0 0, L_0x55f30e0e3d60;  1 drivers
+v0x55f30e0cde10_0 .net "and2", 0 0, L_0x55f30e0e3ea0;  1 drivers
+v0x55f30e0cdee0_0 .net "xor1", 0 0, L_0x55f30e0e3e10;  1 drivers
+S_0x55f30e0ccca0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0ccac0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e3d60 .functor AND 1, L_0x55f30e0e41c0, L_0x55f30e0e42f0, C4<1>, C4<1>;
+L_0x55f30e0e3e10 .functor XOR 1, L_0x55f30e0e41c0, L_0x55f30e0e42f0, C4<0>, C4<0>;
+v0x55f30e0ccf20_0 .net "A", 0 0, L_0x55f30e0e41c0;  alias, 1 drivers
+v0x55f30e0cd000_0 .net "B", 0 0, L_0x55f30e0e42f0;  alias, 1 drivers
+v0x55f30e0cd0c0_0 .net "Carry", 0 0, L_0x55f30e0e3d60;  alias, 1 drivers
+v0x55f30e0cd190_0 .net "Sum", 0 0, L_0x55f30e0e3e10;  alias, 1 drivers
+S_0x55f30e0cd300 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0ccac0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e3ea0 .functor AND 1, L_0x55f30e0e3e10, L_0x55f30e0e4480, C4<1>, C4<1>;
+L_0x55f30e0e4030 .functor XOR 1, L_0x55f30e0e3e10, L_0x55f30e0e4480, C4<0>, C4<0>;
+v0x55f30e0cd570_0 .net "A", 0 0, L_0x55f30e0e3e10;  alias, 1 drivers
+v0x55f30e0cd640_0 .net "B", 0 0, L_0x55f30e0e4480;  alias, 1 drivers
+v0x55f30e0cd6e0_0 .net "Carry", 0 0, L_0x55f30e0e3ea0;  alias, 1 drivers
+v0x55f30e0cd7b0_0 .net "Sum", 0 0, L_0x55f30e0e4030;  alias, 1 drivers
+S_0x55f30e0cdfd0 .scope module, "od1" "overflowDetect" 4 17, 7 1 0, S_0x55f30e0c88c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 2 "opCode";
+    .port_info 1 /INPUT 4 "A";
+    .port_info 2 /INPUT 4 "B";
+    .port_info 3 /INPUT 4 "Y";
+    .port_info 4 /INPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflowDetect";
+L_0x55f30e0e46c0 .functor OR 1, L_0x55f30e0e4750, L_0x55f30e0e47f0, C4<0>, C4<0>;
+L_0x55f30e0e4890 .functor XNOR 1, L_0x55f30e0e4900, L_0x55f30e0e4b00, C4<0>, C4<0>;
+L_0x55f30e0e4bf0 .functor XOR 1, L_0x55f30e0e4c60, L_0x55f30e0e4d50, C4<0>, C4<0>;
+L_0x55f30e0e4e80 .functor XOR 1, L_0x55f30e0e4ef0, L_0x55f30e0e4fe0, C4<0>, C4<0>;
+L_0x55f30e0e5120 .functor AND 1, L_0x55f30e0e4890, L_0x55f30e0e51e0, C4<1>, C4<1>;
+L_0x55f30e0e52d0 .functor AND 1, L_0x55f30e0e4bf0, L_0x55f30e0e5390, C4<1>, C4<1>;
+L_0x55f30e0e54e0 .functor OR 1, L_0x55f30e0e5120, L_0x55f30e0e52d0, C4<0>, C4<0>;
+L_0x55f30e0e5550 .functor AND 1, L_0x55f30e0e54e0, L_0x55f30e0e4e80, C4<1>, C4<1>;
+L_0x55f30e0e56b0 .functor AND 1, L_0x55f30e0e46c0, L_0x55f30e0e5550, C4<1>, C4<1>;
+v0x55f30e0ce2a0_0 .net "A", 3 0, L_0x55f30e0e20e0;  alias, 1 drivers
+v0x55f30e0ce380_0 .net "B", 3 0, L_0x55f30e0e57c0;  alias, 1 drivers
+v0x55f30e0ce460_0 .net "CarryOUT", 0 0, L_0x55f30e0e4110;  alias, 1 drivers
+v0x55f30e0ce500_0 .net "Y", 3 0, L_0x55f30e0e45b0;  alias, 1 drivers
+v0x55f30e0ce5a0_0 .net *"_ivl_1", 0 0, L_0x55f30e0e4750;  1 drivers
+v0x55f30e0ce6d0_0 .net *"_ivl_11", 0 0, L_0x55f30e0e4d50;  1 drivers
+v0x55f30e0ce7b0_0 .net *"_ivl_13", 0 0, L_0x55f30e0e4ef0;  1 drivers
+v0x55f30e0ce890_0 .net *"_ivl_15", 0 0, L_0x55f30e0e4fe0;  1 drivers
+v0x55f30e0ce970_0 .net *"_ivl_17", 0 0, L_0x55f30e0e51e0;  1 drivers
+v0x55f30e0cea50_0 .net *"_ivl_19", 0 0, L_0x55f30e0e5390;  1 drivers
+v0x55f30e0ceb30_0 .net *"_ivl_3", 0 0, L_0x55f30e0e47f0;  1 drivers
+v0x55f30e0cec10_0 .net *"_ivl_5", 0 0, L_0x55f30e0e4900;  1 drivers
+v0x55f30e0cecf0_0 .net *"_ivl_7", 0 0, L_0x55f30e0e4b00;  1 drivers
+v0x55f30e0cedd0_0 .net *"_ivl_9", 0 0, L_0x55f30e0e4c60;  1 drivers
+v0x55f30e0ceeb0_0 .net "addOverflow", 0 0, L_0x55f30e0e5120;  1 drivers
+v0x55f30e0cef70_0 .net "detect1", 0 0, L_0x55f30e0e54e0;  1 drivers
+v0x55f30e0cf030_0 .net "detect2", 0 0, L_0x55f30e0e5550;  1 drivers
+v0x55f30e0cf0f0_0 .net "opC", 0 0, L_0x55f30e0e46c0;  1 drivers
+L_0x7f5d71fc00f0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x55f30e0cf1b0_0 .net "opCode", 1 0, L_0x7f5d71fc00f0;  1 drivers
+v0x55f30e0cf290_0 .net "overflowDetect", 0 0, L_0x55f30e0e56b0;  alias, 1 drivers
+v0x55f30e0cf350_0 .net "sign1", 0 0, L_0x55f30e0e4890;  1 drivers
+v0x55f30e0cf410_0 .net "sign2", 0 0, L_0x55f30e0e4e80;  1 drivers
+v0x55f30e0cf4d0_0 .net "sign3", 0 0, L_0x55f30e0e4bf0;  1 drivers
+v0x55f30e0cf590_0 .net "subOverflow", 0 0, L_0x55f30e0e52d0;  1 drivers
+L_0x55f30e0e4750 .part L_0x7f5d71fc00f0, 0, 1;
+L_0x55f30e0e47f0 .part L_0x7f5d71fc00f0, 1, 1;
+L_0x55f30e0e4900 .part L_0x55f30e0e20e0, 3, 1;
+L_0x55f30e0e4b00 .part L_0x55f30e0e57c0, 3, 1;
+L_0x55f30e0e4c60 .part L_0x55f30e0e20e0, 3, 1;
+L_0x55f30e0e4d50 .part L_0x55f30e0e57c0, 3, 1;
+L_0x55f30e0e4ef0 .part L_0x55f30e0e45b0, 3, 1;
+L_0x55f30e0e4fe0 .part L_0x55f30e0e20e0, 3, 1;
+L_0x55f30e0e51e0 .part L_0x7f5d71fc00f0, 0, 1;
+L_0x55f30e0e5390 .part L_0x7f5d71fc00f0, 1, 1;
+S_0x55f30e0cfe30 .scope module, "add2" "addition" 3 58, 4 1 0, S_0x55f30e070c90;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /INPUT 1 "CarryIN";
+    .port_info 3 /OUTPUT 4 "Y";
+    .port_info 4 /OUTPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflow";
+v0x55f30e0d6fe0_0 .net "A", 3 0, L_0x55f30e0e6160;  alias, 1 drivers
+v0x55f30e0d70c0_0 .net "B", 3 0, L_0x55f30e0e9c70;  1 drivers
+v0x55f30e0d7190_0 .net "Carry4", 3 0, L_0x55f30e0ebad0;  1 drivers
+L_0x7f5d71fc01c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x55f30e0d7260_0 .net "CarryIN", 0 0, L_0x7f5d71fc01c8;  1 drivers
+v0x55f30e0d7300_0 .net "CarryOUT", 0 0, L_0x55f30e0e8710;  1 drivers
+v0x55f30e0d7440_0 .net "Y", 3 0, L_0x55f30e0e8bb0;  1 drivers
+o0x7f5d7200d2d8 .functor BUFZ 1, C4<z>; HiZ drive
+; Elide local net with no drivers, v0x55f30e0d7500_0 name=_ivl_41
+v0x55f30e0d75c0_0 .net "overflow", 0 0, L_0x55f30e0e9b60;  alias, 1 drivers
+L_0x55f30e0e71b0 .part L_0x55f30e0e6160, 0, 1;
+L_0x55f30e0e7370 .part L_0x55f30e0e9c70, 0, 1;
+L_0x55f30e0e7800 .part L_0x55f30e0e6160, 1, 1;
+L_0x55f30e0e7930 .part L_0x55f30e0e9c70, 1, 1;
+L_0x55f30e0e7a60 .part L_0x55f30e0ebad0, 0, 1;
+L_0x55f30e0e7ef0 .part L_0x55f30e0e6160, 2, 1;
+L_0x55f30e0e8020 .part L_0x55f30e0e9c70, 2, 1;
+L_0x55f30e0e81e0 .part L_0x55f30e0ebad0, 1, 1;
+L_0x55f30e0e87c0 .part L_0x55f30e0e6160, 3, 1;
+L_0x55f30e0e88f0 .part L_0x55f30e0e9c70, 3, 1;
+L_0x55f30e0e8a80 .part L_0x55f30e0ebad0, 2, 1;
+L_0x55f30e0e8bb0 .concat8 [ 1 1 1 1], L_0x55f30e0e7040, L_0x55f30e0e76d0, L_0x55f30e0e7dc0, L_0x55f30e0e8630;
+L_0x55f30e0ebad0 .concat [ 1 1 1 1], L_0x55f30e0e7140, L_0x55f30e0e7790, L_0x55f30e0e7e80, o0x7f5d7200d2d8;
+S_0x55f30e0d00b0 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x55f30e0cfe30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e7140 .functor OR 1, L_0x55f30e0e6d20, L_0x55f30e0e6ef0, C4<0>, C4<0>;
+v0x55f30e0d0fe0_0 .net "A", 0 0, L_0x55f30e0e71b0;  1 drivers
+v0x55f30e0d10a0_0 .net "B", 0 0, L_0x55f30e0e7370;  1 drivers
+v0x55f30e0d1170_0 .net "Carry", 0 0, L_0x7f5d71fc01c8;  alias, 1 drivers
+v0x55f30e0d1270_0 .net "CarryO", 0 0, L_0x55f30e0e7140;  1 drivers
+v0x55f30e0d1310_0 .net "Sum", 0 0, L_0x55f30e0e7040;  1 drivers
+v0x55f30e0d1400_0 .net "and1", 0 0, L_0x55f30e0e6d20;  1 drivers
+v0x55f30e0d14d0_0 .net "and2", 0 0, L_0x55f30e0e6ef0;  1 drivers
+v0x55f30e0d15a0_0 .net "xor1", 0 0, L_0x55f30e0e6e80;  1 drivers
+S_0x55f30e0d0340 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d00b0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e6d20 .functor AND 1, L_0x55f30e0e71b0, L_0x55f30e0e7370, C4<1>, C4<1>;
+L_0x55f30e0e6e80 .functor XOR 1, L_0x55f30e0e71b0, L_0x55f30e0e7370, C4<0>, C4<0>;
+v0x55f30e0d05e0_0 .net "A", 0 0, L_0x55f30e0e71b0;  alias, 1 drivers
+v0x55f30e0d06c0_0 .net "B", 0 0, L_0x55f30e0e7370;  alias, 1 drivers
+v0x55f30e0d0780_0 .net "Carry", 0 0, L_0x55f30e0e6d20;  alias, 1 drivers
+v0x55f30e0d0850_0 .net "Sum", 0 0, L_0x55f30e0e6e80;  alias, 1 drivers
+S_0x55f30e0d09c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d00b0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e6ef0 .functor AND 1, L_0x55f30e0e6e80, L_0x7f5d71fc01c8, C4<1>, C4<1>;
+L_0x55f30e0e7040 .functor XOR 1, L_0x55f30e0e6e80, L_0x7f5d71fc01c8, C4<0>, C4<0>;
+v0x55f30e0d0c30_0 .net "A", 0 0, L_0x55f30e0e6e80;  alias, 1 drivers
+v0x55f30e0d0d00_0 .net "B", 0 0, L_0x7f5d71fc01c8;  alias, 1 drivers
+v0x55f30e0d0da0_0 .net "Carry", 0 0, L_0x55f30e0e6ef0;  alias, 1 drivers
+v0x55f30e0d0e70_0 .net "Sum", 0 0, L_0x55f30e0e7040;  alias, 1 drivers
+S_0x55f30e0d1690 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x55f30e0cfe30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e7790 .functor OR 1, L_0x55f30e0e74a0, L_0x55f30e0e7580, C4<0>, C4<0>;
+v0x55f30e0d2570_0 .net "A", 0 0, L_0x55f30e0e7800;  1 drivers
+v0x55f30e0d2630_0 .net "B", 0 0, L_0x55f30e0e7930;  1 drivers
+v0x55f30e0d2700_0 .net "Carry", 0 0, L_0x55f30e0e7a60;  1 drivers
+v0x55f30e0d2800_0 .net "CarryO", 0 0, L_0x55f30e0e7790;  1 drivers
+v0x55f30e0d28a0_0 .net "Sum", 0 0, L_0x55f30e0e76d0;  1 drivers
+v0x55f30e0d2990_0 .net "and1", 0 0, L_0x55f30e0e74a0;  1 drivers
+v0x55f30e0d2a60_0 .net "and2", 0 0, L_0x55f30e0e7580;  1 drivers
+v0x55f30e0d2b30_0 .net "xor1", 0 0, L_0x55f30e0e7510;  1 drivers
+S_0x55f30e0d18f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d1690;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e74a0 .functor AND 1, L_0x55f30e0e7800, L_0x55f30e0e7930, C4<1>, C4<1>;
+L_0x55f30e0e7510 .functor XOR 1, L_0x55f30e0e7800, L_0x55f30e0e7930, C4<0>, C4<0>;
+v0x55f30e0d1b70_0 .net "A", 0 0, L_0x55f30e0e7800;  alias, 1 drivers
+v0x55f30e0d1c50_0 .net "B", 0 0, L_0x55f30e0e7930;  alias, 1 drivers
+v0x55f30e0d1d10_0 .net "Carry", 0 0, L_0x55f30e0e74a0;  alias, 1 drivers
+v0x55f30e0d1de0_0 .net "Sum", 0 0, L_0x55f30e0e7510;  alias, 1 drivers
+S_0x55f30e0d1f50 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d1690;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e7580 .functor AND 1, L_0x55f30e0e7510, L_0x55f30e0e7a60, C4<1>, C4<1>;
+L_0x55f30e0e76d0 .functor XOR 1, L_0x55f30e0e7510, L_0x55f30e0e7a60, C4<0>, C4<0>;
+v0x55f30e0d21c0_0 .net "A", 0 0, L_0x55f30e0e7510;  alias, 1 drivers
+v0x55f30e0d2290_0 .net "B", 0 0, L_0x55f30e0e7a60;  alias, 1 drivers
+v0x55f30e0d2330_0 .net "Carry", 0 0, L_0x55f30e0e7580;  alias, 1 drivers
+v0x55f30e0d2400_0 .net "Sum", 0 0, L_0x55f30e0e76d0;  alias, 1 drivers
+S_0x55f30e0d2c20 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x55f30e0cfe30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e7e80 .functor OR 1, L_0x55f30e0e7b90, L_0x55f30e0e7c70, C4<0>, C4<0>;
+v0x55f30e0d3b10_0 .net "A", 0 0, L_0x55f30e0e7ef0;  1 drivers
+v0x55f30e0d3bd0_0 .net "B", 0 0, L_0x55f30e0e8020;  1 drivers
+v0x55f30e0d3ca0_0 .net "Carry", 0 0, L_0x55f30e0e81e0;  1 drivers
+v0x55f30e0d3da0_0 .net "CarryO", 0 0, L_0x55f30e0e7e80;  1 drivers
+v0x55f30e0d3e40_0 .net "Sum", 0 0, L_0x55f30e0e7dc0;  1 drivers
+v0x55f30e0d3f30_0 .net "and1", 0 0, L_0x55f30e0e7b90;  1 drivers
+v0x55f30e0d4000_0 .net "and2", 0 0, L_0x55f30e0e7c70;  1 drivers
+v0x55f30e0d40d0_0 .net "xor1", 0 0, L_0x55f30e0e7c00;  1 drivers
+S_0x55f30e0d2eb0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d2c20;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e7b90 .functor AND 1, L_0x55f30e0e7ef0, L_0x55f30e0e8020, C4<1>, C4<1>;
+L_0x55f30e0e7c00 .functor XOR 1, L_0x55f30e0e7ef0, L_0x55f30e0e8020, C4<0>, C4<0>;
+v0x55f30e0d3130_0 .net "A", 0 0, L_0x55f30e0e7ef0;  alias, 1 drivers
+v0x55f30e0d31f0_0 .net "B", 0 0, L_0x55f30e0e8020;  alias, 1 drivers
+v0x55f30e0d32b0_0 .net "Carry", 0 0, L_0x55f30e0e7b90;  alias, 1 drivers
+v0x55f30e0d3380_0 .net "Sum", 0 0, L_0x55f30e0e7c00;  alias, 1 drivers
+S_0x55f30e0d34f0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d2c20;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e7c70 .functor AND 1, L_0x55f30e0e7c00, L_0x55f30e0e81e0, C4<1>, C4<1>;
+L_0x55f30e0e7dc0 .functor XOR 1, L_0x55f30e0e7c00, L_0x55f30e0e81e0, C4<0>, C4<0>;
+v0x55f30e0d3760_0 .net "A", 0 0, L_0x55f30e0e7c00;  alias, 1 drivers
+v0x55f30e0d3830_0 .net "B", 0 0, L_0x55f30e0e81e0;  alias, 1 drivers
+v0x55f30e0d38d0_0 .net "Carry", 0 0, L_0x55f30e0e7c70;  alias, 1 drivers
+v0x55f30e0d39a0_0 .net "Sum", 0 0, L_0x55f30e0e7dc0;  alias, 1 drivers
+S_0x55f30e0d41c0 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x55f30e0cfe30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Carry";
+    .port_info 3 /OUTPUT 1 "Sum";
+    .port_info 4 /OUTPUT 1 "CarryO";
+L_0x55f30e0e8710 .functor OR 1, L_0x55f30e0e8360, L_0x55f30e0e84a0, C4<0>, C4<0>;
+v0x55f30e0d50a0_0 .net "A", 0 0, L_0x55f30e0e87c0;  1 drivers
+v0x55f30e0d5160_0 .net "B", 0 0, L_0x55f30e0e88f0;  1 drivers
+v0x55f30e0d5230_0 .net "Carry", 0 0, L_0x55f30e0e8a80;  1 drivers
+v0x55f30e0d5330_0 .net "CarryO", 0 0, L_0x55f30e0e8710;  alias, 1 drivers
+v0x55f30e0d53d0_0 .net "Sum", 0 0, L_0x55f30e0e8630;  1 drivers
+v0x55f30e0d54c0_0 .net "and1", 0 0, L_0x55f30e0e8360;  1 drivers
+v0x55f30e0d5590_0 .net "and2", 0 0, L_0x55f30e0e84a0;  1 drivers
+v0x55f30e0d5660_0 .net "xor1", 0 0, L_0x55f30e0e8410;  1 drivers
+S_0x55f30e0d4420 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d41c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e8360 .functor AND 1, L_0x55f30e0e87c0, L_0x55f30e0e88f0, C4<1>, C4<1>;
+L_0x55f30e0e8410 .functor XOR 1, L_0x55f30e0e87c0, L_0x55f30e0e88f0, C4<0>, C4<0>;
+v0x55f30e0d46a0_0 .net "A", 0 0, L_0x55f30e0e87c0;  alias, 1 drivers
+v0x55f30e0d4780_0 .net "B", 0 0, L_0x55f30e0e88f0;  alias, 1 drivers
+v0x55f30e0d4840_0 .net "Carry", 0 0, L_0x55f30e0e8360;  alias, 1 drivers
+v0x55f30e0d4910_0 .net "Sum", 0 0, L_0x55f30e0e8410;  alias, 1 drivers
+S_0x55f30e0d4a80 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d41c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Sum";
+    .port_info 3 /OUTPUT 1 "Carry";
+L_0x55f30e0e84a0 .functor AND 1, L_0x55f30e0e8410, L_0x55f30e0e8a80, C4<1>, C4<1>;
+L_0x55f30e0e8630 .functor XOR 1, L_0x55f30e0e8410, L_0x55f30e0e8a80, C4<0>, C4<0>;
+v0x55f30e0d4cf0_0 .net "A", 0 0, L_0x55f30e0e8410;  alias, 1 drivers
+v0x55f30e0d4dc0_0 .net "B", 0 0, L_0x55f30e0e8a80;  alias, 1 drivers
+v0x55f30e0d4e60_0 .net "Carry", 0 0, L_0x55f30e0e84a0;  alias, 1 drivers
+v0x55f30e0d4f30_0 .net "Sum", 0 0, L_0x55f30e0e8630;  alias, 1 drivers
+S_0x55f30e0d5750 .scope module, "od1" "overflowDetect" 4 17, 7 1 0, S_0x55f30e0cfe30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 2 "opCode";
+    .port_info 1 /INPUT 4 "A";
+    .port_info 2 /INPUT 4 "B";
+    .port_info 3 /INPUT 4 "Y";
+    .port_info 4 /INPUT 1 "CarryOUT";
+    .port_info 5 /OUTPUT 1 "overflowDetect";
+L_0x55f30e0e8cc0 .functor OR 1, L_0x55f30e0e8d50, L_0x55f30e0e8df0, C4<0>, C4<0>;
+L_0x55f30e0e8e90 .functor XNOR 1, L_0x55f30e0e8f00, L_0x55f30e0e8ff0, C4<0>, C4<0>;
+L_0x55f30e0e90e0 .functor XOR 1, L_0x55f30e0e9150, L_0x55f30e0e9240, C4<0>, C4<0>;
+L_0x55f30e0e9330 .functor XOR 1, L_0x55f30e0e93a0, L_0x55f30e0e9490, C4<0>, C4<0>;
+L_0x55f30e0e95d0 .functor AND 1, L_0x55f30e0e8e90, L_0x55f30e0e9690, C4<1>, C4<1>;
+L_0x55f30e0e9780 .functor AND 1, L_0x55f30e0e90e0, L_0x55f30e0e9840, C4<1>, C4<1>;
+L_0x55f30e0e9990 .functor OR 1, L_0x55f30e0e95d0, L_0x55f30e0e9780, C4<0>, C4<0>;
+L_0x55f30e0e9a00 .functor AND 1, L_0x55f30e0e9990, L_0x55f30e0e9330, C4<1>, C4<1>;
+L_0x55f30e0e9b60 .functor AND 1, L_0x55f30e0e8cc0, L_0x55f30e0e9a00, C4<1>, C4<1>;
+v0x55f30e0d5a20_0 .net "A", 3 0, L_0x55f30e0e6160;  alias, 1 drivers
+v0x55f30e0d5b00_0 .net "B", 3 0, L_0x55f30e0e9c70;  alias, 1 drivers
+v0x55f30e0d5be0_0 .net "CarryOUT", 0 0, L_0x55f30e0e8710;  alias, 1 drivers
+v0x55f30e0d5c80_0 .net "Y", 3 0, L_0x55f30e0e8bb0;  alias, 1 drivers
+v0x55f30e0d5d20_0 .net *"_ivl_1", 0 0, L_0x55f30e0e8d50;  1 drivers
+v0x55f30e0d5e50_0 .net *"_ivl_11", 0 0, L_0x55f30e0e9240;  1 drivers
+v0x55f30e0d5f30_0 .net *"_ivl_13", 0 0, L_0x55f30e0e93a0;  1 drivers
+v0x55f30e0d6010_0 .net *"_ivl_15", 0 0, L_0x55f30e0e9490;  1 drivers
+v0x55f30e0d60f0_0 .net *"_ivl_17", 0 0, L_0x55f30e0e9690;  1 drivers
+v0x55f30e0d61d0_0 .net *"_ivl_19", 0 0, L_0x55f30e0e9840;  1 drivers
+v0x55f30e0d62b0_0 .net *"_ivl_3", 0 0, L_0x55f30e0e8df0;  1 drivers
+v0x55f30e0d6390_0 .net *"_ivl_5", 0 0, L_0x55f30e0e8f00;  1 drivers
+v0x55f30e0d6470_0 .net *"_ivl_7", 0 0, L_0x55f30e0e8ff0;  1 drivers
+v0x55f30e0d6550_0 .net *"_ivl_9", 0 0, L_0x55f30e0e9150;  1 drivers
+v0x55f30e0d6630_0 .net "addOverflow", 0 0, L_0x55f30e0e95d0;  1 drivers
+v0x55f30e0d66f0_0 .net "detect1", 0 0, L_0x55f30e0e9990;  1 drivers
+v0x55f30e0d67b0_0 .net "detect2", 0 0, L_0x55f30e0e9a00;  1 drivers
+v0x55f30e0d6980_0 .net "opC", 0 0, L_0x55f30e0e8cc0;  1 drivers
+L_0x7f5d71fc0180 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x55f30e0d6a40_0 .net "opCode", 1 0, L_0x7f5d71fc0180;  1 drivers
+v0x55f30e0d6b20_0 .net "overflowDetect", 0 0, L_0x55f30e0e9b60;  alias, 1 drivers
+v0x55f30e0d6be0_0 .net "sign1", 0 0, L_0x55f30e0e8e90;  1 drivers
+v0x55f30e0d6ca0_0 .net "sign2", 0 0, L_0x55f30e0e9330;  1 drivers
+v0x55f30e0d6d60_0 .net "sign3", 0 0, L_0x55f30e0e90e0;  1 drivers
+v0x55f30e0d6e20_0 .net "subOverflow", 0 0, L_0x55f30e0e9780;  1 drivers
+L_0x55f30e0e8d50 .part L_0x7f5d71fc0180, 0, 1;
+L_0x55f30e0e8df0 .part L_0x7f5d71fc0180, 1, 1;
+L_0x55f30e0e8f00 .part L_0x55f30e0e6160, 3, 1;
+L_0x55f30e0e8ff0 .part L_0x55f30e0e9c70, 3, 1;
+L_0x55f30e0e9150 .part L_0x55f30e0e6160, 3, 1;
+L_0x55f30e0e9240 .part L_0x55f30e0e9c70, 3, 1;
+L_0x55f30e0e93a0 .part L_0x55f30e0e8bb0, 3, 1;
+L_0x55f30e0e9490 .part L_0x55f30e0e6160, 3, 1;
+L_0x55f30e0e9690 .part L_0x7f5d71fc0180, 0, 1;
+L_0x55f30e0e9840 .part L_0x7f5d71fc0180, 1, 1;
+    .scope S_0x55f30e07afd0;
+T_0 ;
+    %vpi_call 2 12 "$dumpfile", "multiplier.vcd" {0 0 0};
+    %vpi_call 2 13 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55f30e0dc920_0, 0, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55f30e0dc9e0_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55f30e0dc920_0, 0, 4;
+    %pushi/vec4 8, 0, 4;
+    %store/vec4 v0x55f30e0dc9e0_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 8, 0, 4;
+    %store/vec4 v0x55f30e0dc920_0, 0, 4;
+    %pushi/vec4 8, 0, 4;
+    %store/vec4 v0x55f30e0dc9e0_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 7, 0, 4;
+    %store/vec4 v0x55f30e0dc920_0, 0, 4;
+    %pushi/vec4 7, 0, 4;
+    %store/vec4 v0x55f30e0dc9e0_0, 0, 4;
+    %delay 2, 0;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55f30e0dc920_0, 0, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55f30e0dc9e0_0, 0, 4;
+    %delay 2, 0;
+    %vpi_call 2 19 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 8;
+    "N/A";
+    "<interactive>";
+    "multiplierTB.v";
+    "multiplier.v";
+    "addition.v";
+    "fulladder.v";
+    "halfadder.v";
+    "overflowDetect.v";
--- a/verilog/ALU0.2/multiplier.v
+++ b/verilog/ALU0.2/multiplier.v
@@ -0,0 +1,76 @@
+module multiplier (
+    input [3:0] A, B,
+    output [7:0] Y
+);
+
+wire [3:0] b0, a0, a1, a2;
+wire [4:0] S0, S1, S2;
+wire carry0, carry1, carry2;
+wire overflow0, overflow1, overflow2;
+
+// Partial product generation
+and (Y[0], A[0], B[0]); // LSB of the result
+
+// Generate partial products for B[0] and B[1]
+and ab00 (b0[0], A[1], B[0]);
+and ab01 (b0[1], A[2], B[0]);
+and ab02 (b0[2], A[3], B[0]);
+not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
+
+and aa00 (a0[0], A[0], B[1]);
+and aa01 (a0[1], A[1], B[1]);
+and aa02 (a0[2], A[2], B[1]);
+and aa03 (a0[3], A[3], B[1]);
+
+// First addition
+addition add0 (
+    .A(a0),
+    .B(b0),
+    .CarryIN(1'b0),
+    .Y(S0[3:0]),
+    .CarryOUT(S0[4]),
+    .overflow(overflow0)
+);
+
+// Generate partial products for B[2]
+and aa10 (a1[0], A[0], B[2]);
+and aa11 (a1[1], A[1], B[2]);
+and aa12 (a1[2], A[2], B[2]);
+and aa13 (a1[3], A[3], B[2]);
+
+// Second addition
+addition add1 (
+    .A(a1),
+    .B(S0[4:1]),
+    .CarryIN(1'b0),
+    .Y(S1[3:0]),
+    .CarryOUT(S1[4]),
+    .overflow(overflow1)
+);
+
+// Generate partial products for B[3]
+and aa20 (a2[0], A[0], B[3]);
+and aa21 (a2[1], A[1], B[3]);
+and aa22 (a2[2], A[2], B[3]);
+and aa23 (a2[3], A[3], B[3]);
+
+// Third addition
+addition add2 (
+    .A(a2),
+    .B(S1[4:1]),
+    .CarryIN(1'b0),
+    .Y(S2[3:0]),
+    .CarryOUT(S2[4]),
+    .overflow(overflow2)
+);
+
+// Combine results into the final output Y
+or o01 (Y[1], S0[0], 1'b0);
+or o02 (Y[2], S1[0], 1'b0);
+or o03 (Y[3], S2[0], 1'b0);
+or o04 (Y[4], S2[1], 1'b0);
+or o05 (Y[5], S2[2], 1'b0);
+or o06 (Y[6], S2[3], 1'b0);
+or o07 (Y[7], S2[4], 1'b0);
+
+endmodule
--- a/verilog/ALU0.2/multiplier.vcd
+++ b/verilog/ALU0.2/multiplier.vcd
@@ -0,0 +1,769 @@
+$date
+	Fri Dec 20 19:46:49 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module multiplierTB $end
+$var wire 8 ! Y [7:0] $end
+$var reg 4 " A [3:0] $end
+$var reg 4 # B [3:0] $end
+$scope module uut $end
+$var wire 4 $ A [3:0] $end
+$var wire 4 % B [3:0] $end
+$var wire 1 & overflow2 $end
+$var wire 1 ' overflow1 $end
+$var wire 1 ( overflow0 $end
+$var wire 4 ) b0 [3:0] $end
+$var wire 4 * a2 [3:0] $end
+$var wire 4 + a1 [3:0] $end
+$var wire 4 , a0 [3:0] $end
+$var wire 8 - Y [7:0] $end
+$var wire 5 . S2 [4:0] $end
+$var wire 5 / S1 [4:0] $end
+$var wire 5 0 S0 [4:0] $end
+$scope module add0 $end
+$var wire 4 1 A [3:0] $end
+$var wire 4 2 B [3:0] $end
+$var wire 1 3 CarryIN $end
+$var wire 1 ( overflow $end
+$var wire 4 4 Y [3:0] $end
+$var wire 1 5 CarryOUT $end
+$var wire 4 6 Carry4 [3:0] $end
+$scope module f0 $end
+$var wire 1 7 A $end
+$var wire 1 8 B $end
+$var wire 1 3 Carry $end
+$var wire 1 9 CarryO $end
+$var wire 1 : xor1 $end
+$var wire 1 ; and2 $end
+$var wire 1 < and1 $end
+$var wire 1 = Sum $end
+$scope module h1 $end
+$var wire 1 7 A $end
+$var wire 1 8 B $end
+$var wire 1 < Carry $end
+$var wire 1 : Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 : A $end
+$var wire 1 3 B $end
+$var wire 1 ; Carry $end
+$var wire 1 = Sum $end
+$upscope $end
+$upscope $end
+$scope module f1 $end
+$var wire 1 > A $end
+$var wire 1 ? B $end
+$var wire 1 @ Carry $end
+$var wire 1 A CarryO $end
+$var wire 1 B xor1 $end
+$var wire 1 C and2 $end
+$var wire 1 D and1 $end
+$var wire 1 E Sum $end
+$scope module h1 $end
+$var wire 1 > A $end
+$var wire 1 ? B $end
+$var wire 1 D Carry $end
+$var wire 1 B Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 B A $end
+$var wire 1 @ B $end
+$var wire 1 C Carry $end
+$var wire 1 E Sum $end
+$upscope $end
+$upscope $end
+$scope module f2 $end
+$var wire 1 F A $end
+$var wire 1 G B $end
+$var wire 1 H Carry $end
+$var wire 1 I CarryO $end
+$var wire 1 J xor1 $end
+$var wire 1 K and2 $end
+$var wire 1 L and1 $end
+$var wire 1 M Sum $end
+$scope module h1 $end
+$var wire 1 F A $end
+$var wire 1 G B $end
+$var wire 1 L Carry $end
+$var wire 1 J Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 J A $end
+$var wire 1 H B $end
+$var wire 1 K Carry $end
+$var wire 1 M Sum $end
+$upscope $end
+$upscope $end
+$scope module f3 $end
+$var wire 1 N A $end
+$var wire 1 O B $end
+$var wire 1 P Carry $end
+$var wire 1 5 CarryO $end
+$var wire 1 Q xor1 $end
+$var wire 1 R and2 $end
+$var wire 1 S and1 $end
+$var wire 1 T Sum $end
+$scope module h1 $end
+$var wire 1 N A $end
+$var wire 1 O B $end
+$var wire 1 S Carry $end
+$var wire 1 Q Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 Q A $end
+$var wire 1 P B $end
+$var wire 1 R Carry $end
+$var wire 1 T Sum $end
+$upscope $end
+$upscope $end
+$scope module od1 $end
+$var wire 4 U A [3:0] $end
+$var wire 4 V B [3:0] $end
+$var wire 1 5 CarryOUT $end
+$var wire 4 W Y [3:0] $end
+$var wire 1 X addOverflow $end
+$var wire 1 Y detect1 $end
+$var wire 1 Z detect2 $end
+$var wire 1 [ opC $end
+$var wire 2 \ opCode [1:0] $end
+$var wire 1 ( overflowDetect $end
+$var wire 1 ] sign1 $end
+$var wire 1 ^ sign2 $end
+$var wire 1 _ sign3 $end
+$var wire 1 ` subOverflow $end
+$upscope $end
+$upscope $end
+$scope module add1 $end
+$var wire 4 a A [3:0] $end
+$var wire 4 b B [3:0] $end
+$var wire 1 c CarryIN $end
+$var wire 1 ' overflow $end
+$var wire 4 d Y [3:0] $end
+$var wire 1 e CarryOUT $end
+$var wire 4 f Carry4 [3:0] $end
+$scope module f0 $end
+$var wire 1 g A $end
+$var wire 1 h B $end
+$var wire 1 c Carry $end
+$var wire 1 i CarryO $end
+$var wire 1 j xor1 $end
+$var wire 1 k and2 $end
+$var wire 1 l and1 $end
+$var wire 1 m Sum $end
+$scope module h1 $end
+$var wire 1 g A $end
+$var wire 1 h B $end
+$var wire 1 l Carry $end
+$var wire 1 j Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 j A $end
+$var wire 1 c B $end
+$var wire 1 k Carry $end
+$var wire 1 m Sum $end
+$upscope $end
+$upscope $end
+$scope module f1 $end
+$var wire 1 n A $end
+$var wire 1 o B $end
+$var wire 1 p Carry $end
+$var wire 1 q CarryO $end
+$var wire 1 r xor1 $end
+$var wire 1 s and2 $end
+$var wire 1 t and1 $end
+$var wire 1 u Sum $end
+$scope module h1 $end
+$var wire 1 n A $end
+$var wire 1 o B $end
+$var wire 1 t Carry $end
+$var wire 1 r Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 r A $end
+$var wire 1 p B $end
+$var wire 1 s Carry $end
+$var wire 1 u Sum $end
+$upscope $end
+$upscope $end
+$scope module f2 $end
+$var wire 1 v A $end
+$var wire 1 w B $end
+$var wire 1 x Carry $end
+$var wire 1 y CarryO $end
+$var wire 1 z xor1 $end
+$var wire 1 { and2 $end
+$var wire 1 | and1 $end
+$var wire 1 } Sum $end
+$scope module h1 $end
+$var wire 1 v A $end
+$var wire 1 w B $end
+$var wire 1 | Carry $end
+$var wire 1 z Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 z A $end
+$var wire 1 x B $end
+$var wire 1 { Carry $end
+$var wire 1 } Sum $end
+$upscope $end
+$upscope $end
+$scope module f3 $end
+$var wire 1 ~ A $end
+$var wire 1 !" B $end
+$var wire 1 "" Carry $end
+$var wire 1 e CarryO $end
+$var wire 1 #" xor1 $end
+$var wire 1 $" and2 $end
+$var wire 1 %" and1 $end
+$var wire 1 &" Sum $end
+$scope module h1 $end
+$var wire 1 ~ A $end
+$var wire 1 !" B $end
+$var wire 1 %" Carry $end
+$var wire 1 #" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 #" A $end
+$var wire 1 "" B $end
+$var wire 1 $" Carry $end
+$var wire 1 &" Sum $end
+$upscope $end
+$upscope $end
+$scope module od1 $end
+$var wire 4 '" A [3:0] $end
+$var wire 4 (" B [3:0] $end
+$var wire 1 e CarryOUT $end
+$var wire 4 )" Y [3:0] $end
+$var wire 1 *" addOverflow $end
+$var wire 1 +" detect1 $end
+$var wire 1 ," detect2 $end
+$var wire 1 -" opC $end
+$var wire 2 ." opCode [1:0] $end
+$var wire 1 ' overflowDetect $end
+$var wire 1 /" sign1 $end
+$var wire 1 0" sign2 $end
+$var wire 1 1" sign3 $end
+$var wire 1 2" subOverflow $end
+$upscope $end
+$upscope $end
+$scope module add2 $end
+$var wire 4 3" A [3:0] $end
+$var wire 4 4" B [3:0] $end
+$var wire 1 5" CarryIN $end
+$var wire 1 & overflow $end
+$var wire 4 6" Y [3:0] $end
+$var wire 1 7" CarryOUT $end
+$var wire 4 8" Carry4 [3:0] $end
+$scope module f0 $end
+$var wire 1 9" A $end
+$var wire 1 :" B $end
+$var wire 1 5" Carry $end
+$var wire 1 ;" CarryO $end
+$var wire 1 <" xor1 $end
+$var wire 1 =" and2 $end
+$var wire 1 >" and1 $end
+$var wire 1 ?" Sum $end
+$scope module h1 $end
+$var wire 1 9" A $end
+$var wire 1 :" B $end
+$var wire 1 >" Carry $end
+$var wire 1 <" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 <" A $end
+$var wire 1 5" B $end
+$var wire 1 =" Carry $end
+$var wire 1 ?" Sum $end
+$upscope $end
+$upscope $end
+$scope module f1 $end
+$var wire 1 @" A $end
+$var wire 1 A" B $end
+$var wire 1 B" Carry $end
+$var wire 1 C" CarryO $end
+$var wire 1 D" xor1 $end
+$var wire 1 E" and2 $end
+$var wire 1 F" and1 $end
+$var wire 1 G" Sum $end
+$scope module h1 $end
+$var wire 1 @" A $end
+$var wire 1 A" B $end
+$var wire 1 F" Carry $end
+$var wire 1 D" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 D" A $end
+$var wire 1 B" B $end
+$var wire 1 E" Carry $end
+$var wire 1 G" Sum $end
+$upscope $end
+$upscope $end
+$scope module f2 $end
+$var wire 1 H" A $end
+$var wire 1 I" B $end
+$var wire 1 J" Carry $end
+$var wire 1 K" CarryO $end
+$var wire 1 L" xor1 $end
+$var wire 1 M" and2 $end
+$var wire 1 N" and1 $end
+$var wire 1 O" Sum $end
+$scope module h1 $end
+$var wire 1 H" A $end
+$var wire 1 I" B $end
+$var wire 1 N" Carry $end
+$var wire 1 L" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 L" A $end
+$var wire 1 J" B $end
+$var wire 1 M" Carry $end
+$var wire 1 O" Sum $end
+$upscope $end
+$upscope $end
+$scope module f3 $end
+$var wire 1 P" A $end
+$var wire 1 Q" B $end
+$var wire 1 R" Carry $end
+$var wire 1 7" CarryO $end
+$var wire 1 S" xor1 $end
+$var wire 1 T" and2 $end
+$var wire 1 U" and1 $end
+$var wire 1 V" Sum $end
+$scope module h1 $end
+$var wire 1 P" A $end
+$var wire 1 Q" B $end
+$var wire 1 U" Carry $end
+$var wire 1 S" Sum $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 S" A $end
+$var wire 1 R" B $end
+$var wire 1 T" Carry $end
+$var wire 1 V" Sum $end
+$upscope $end
+$upscope $end
+$scope module od1 $end
+$var wire 4 W" A [3:0] $end
+$var wire 4 X" B [3:0] $end
+$var wire 1 7" CarryOUT $end
+$var wire 4 Y" Y [3:0] $end
+$var wire 1 Z" addOverflow $end
+$var wire 1 [" detect1 $end
+$var wire 1 \" detect2 $end
+$var wire 1 ]" opC $end
+$var wire 2 ^" opCode [1:0] $end
+$var wire 1 & overflowDetect $end
+$var wire 1 _" sign1 $end
+$var wire 1 `" sign2 $end
+$var wire 1 a" sign3 $end
+$var wire 1 b" subOverflow $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0b"
+0a"
+0`"
+1_"
+b1 ^"
+1]"
+0\"
+1["
+1Z"
+b0 Y"
+b0 X"
+b0 W"
+0V"
+0U"
+0T"
+0S"
+0R"
+0Q"
+0P"
+0O"
+0N"
+0M"
+0L"
+0K"
+0J"
+0I"
+0H"
+0G"
+0F"
+0E"
+0D"
+0C"
+0B"
+0A"
+0@"
+0?"
+0>"
+0="
+0<"
+0;"
+0:"
+09"
+bz000 8"
+07"
+b0 6"
+05"
+b0 4"
+b0 3"
+02"
+01"
+00"
+1/"
+b1 ."
+1-"
+0,"
+1+"
+1*"
+b0 )"
+b0 ("
+b0 '"
+0&"
+0%"
+0$"
+0#"
+0""
+0!"
+0~
+0}
+0|
+0{
+0z
+0y
+0x
+0w
+0v
+0u
+0t
+0s
+0r
+0q
+0p
+0o
+0n
+0m
+0l
+0k
+0j
+0i
+0h
+0g
+bz000 f
+0e
+b0 d
+0c
+b0 b
+b0 a
+0`
+0_
+0^
+1]
+b1 \
+1[
+0Z
+1Y
+1X
+b0 W
+b0 V
+b0 U
+0T
+0S
+0R
+0Q
+0P
+0O
+0N
+0M
+0L
+0K
+0J
+0I
+0H
+0G
+0F
+0E
+0D
+0C
+0B
+0A
+0@
+0?
+0>
+0=
+0<
+0;
+0:
+09
+08
+07
+bz000 6
+05
+b0 4
+03
+b0 2
+b0 1
+b0 0
+b0 /
+b0 .
+b0 -
+b0 ,
+b0 +
+b0 *
+b0 )
+0(
+0'
+0&
+b0 %
+b0 $
+b0 #
+b0 "
+b0 !
+$end
+#2
+b1000 #
+b1000 %
+#4
+b1000000 !
+b1000000 -
+0["
+0&
+b1000 .
+b1000 6"
+b1000 Y"
+1V"
+0Z"
+0\"
+1S"
+0_"
+1a"
+0`"
+1P"
+b1000 *
+b1000 3"
+b1000 W"
+b1000 "
+b1000 $
+#6
+1'
+1O"
+1,"
+1L"
+10"
+1I"
+1(
+1&"
+1Z
+1|
+1s
+1""
+1^
+1w
+1p
+1y
+1i
+0{
+1T
+1l
+1x
+1P
+1h
+bz111 f
+1q
+0?"
+1G"
+1I
+0t
+0<"
+1D"
+0&
+1E
+1K
+0o
+0:"
+1A"
+0\"
+1@
+1H
+b101 b
+b101 ("
+b110 4"
+b110 X"
+1["
+19
+bz111 6
+1A
+b1010 0
+b1010 4
+b1010 W
+0M
+0m
+0u
+b1100 /
+b1100 d
+b1100 )"
+1}
+b110 .
+b110 6"
+b110 Y"
+0V"
+1Z"
+1<
+1D
+1J
+0j
+1r
+0z
+0S"
+1_"
+0a"
+0`"
+18
+1?
+17
+1>
+1F
+1g
+1n
+1v
+0P"
+b110001 !
+b110001 -
+b11 )
+b11 2
+b11 V
+b111 ,
+b111 1
+b111 U
+b111 +
+b111 a
+b111 '"
+b0 *
+b0 3"
+b0 W"
+b111 #
+b111 %
+b111 "
+b111 $
+#8
+1E"
+1B"
+1;"
+1>"
+1:"
+0A"
+1%"
+0s
+1u
+1{
+0}
+1U"
+0M"
+17"
+1!"
+1t
+0r
+0|
+1z
+1Q"
+0T"
+1o
+0w
+1I"
+b11100001 !
+b11100001 -
+1J"
+1R"
+15
+b1011 b
+b1011 ("
+0Y
+0(
+1e
+b1101 4"
+b1101 X"
+1+"
+0'
+1["
+0&
+0?"
+1C"
+0G"
+bz111 8"
+1K"
+1O"
+0K
+1M
+1R
+b10110 0
+b110 4
+b110 W
+0T
+0X
+0Z
+0$"
+b11010 /
+b1010 d
+b1010 )"
+1&"
+1*"
+0,"
+b11100 .
+b1100 6"
+b1100 Y"
+1V"
+1Z"
+0\"
+0<"
+0F"
+1D"
+1N"
+0L"
+1L
+0J
+1Q
+0]
+1_
+1^
+0#"
+1/"
+01"
+00"
+0S"
+1_"
+0a"
+0`"
+19"
+1@"
+1H"
+1G
+1N
+1~
+1P"
+b111 )
+b111 2
+b111 V
+b1111 ,
+b1111 1
+b1111 U
+b1111 +
+b1111 a
+b1111 '"
+b1111 *
+b1111 3"
+b1111 W"
+b1111 #
+b1111 %
+b1111 "
+b1111 $
+#10
--- a/verilog/ALU0.2/multiplier.vcdZone.Identifier
+++ b/verilog/ALU0.2/multiplier.vcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/multiplier.vZone.Identifier
+++ b/verilog/ALU0.2/multiplier.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/multiplierTB.v
+++ b/verilog/ALU0.2/multiplierTB.v
@@ -0,0 +1,22 @@
+module multiplierTB();
+reg [3:0] A, B;
+wire [7:0] Y;
+
+multiplier uut(
+    .A(A),
+    .B(B),
+    .Y(Y)
+);
+
+initial begin
+    $dumpfile("multiplier.vcd");
+    $dumpvars;
+    A = 4'b0000; B = 4'b0000; #2;
+    A = 4'b0000; B = 4'b1000; #2;
+    A = 4'b1000; B = 4'b1000; #2;
+    A = 4'b0111; B = 4'b0111; #2;
+    A = 4'b1111; B = 4'b1111; #2;
+    $finish;
+end
+
+endmodule
--- a/verilog/ALU0.2/multiplierTB.vZone.Identifier
+++ b/verilog/ALU0.2/multiplierTB.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/multiplierZone.Identifier
+++ b/verilog/ALU0.2/multiplierZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/opCode
+++ b/verilog/ALU0.2/opCode
@@ -0,0 +1,111 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x5602ec702f00 .scope module, "opCodeTB" "opCodeTB" 2 1;
+ .timescale 0 0;
+v0x5602ec71a9e0_0 .var "A", 2 0;
+v0x5602ec71aaa0_0 .net "opCode", 7 0, L_0x5602ec71c020;  1 drivers
+S_0x5602ec703090 .scope module, "uut" "opCode" 2 6, 3 1 0, S_0x5602ec702f00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 3 "A";
+    .port_info 1 /OUTPUT 8 "opCode";
+L_0x5602ec71ab70 .functor NOT 1, L_0x5602ec71ac40, C4<0>, C4<0>, C4<0>;
+L_0x5602ec71ad30 .functor NOT 1, L_0x5602ec71adc0, C4<0>, C4<0>, C4<0>;
+L_0x5602ec71aeb0 .functor NOT 1, L_0x5602ec71af50, C4<0>, C4<0>, C4<0>;
+L_0x5602ec71b040 .functor AND 1, L_0x5602ec71b140, L_0x5602ec71b210, C4<1>, C4<1>;
+L_0x5602ec71b300 .functor AND 1, L_0x5602ec71ab70, L_0x5602ec71b3c0, C4<1>, C4<1>;
+L_0x5602ec71b4f0 .functor AND 1, L_0x5602ec71b5f0, L_0x5602ec71ad30, C4<1>, C4<1>;
+L_0x5602ec71b6e0 .functor AND 1, L_0x5602ec71ab70, L_0x5602ec71ad30, C4<1>, C4<1>;
+L_0x5602ec71b750 .functor AND 1, L_0x5602ec71b6e0, L_0x5602ec71aeb0, C4<1>, C4<1>;
+L_0x5602ec71b8b0 .functor AND 1, L_0x5602ec71b6e0, L_0x5602ec71b920, C4<1>, C4<1>;
+L_0x5602ec71ba60 .functor AND 1, L_0x5602ec71b300, L_0x5602ec71aeb0, C4<1>, C4<1>;
+L_0x5602ec71bb80 .functor AND 1, L_0x5602ec71b300, L_0x5602ec71bbf0, C4<1>, C4<1>;
+L_0x5602ec71bc90 .functor AND 1, L_0x5602ec71b4f0, L_0x5602ec71aeb0, C4<1>, C4<1>;
+L_0x5602ec71bdc0 .functor AND 1, L_0x5602ec71b4f0, L_0x5602ec71be30, C4<1>, C4<1>;
+L_0x5602ec71bf30 .functor AND 1, L_0x5602ec71b040, L_0x5602ec71aeb0, C4<1>, C4<1>;
+L_0x5602ec71bd50 .functor AND 1, L_0x5602ec71b040, L_0x5602ec71c3e0, C4<1>, C4<1>;
+v0x5602ec6ef910_0 .net "A", 2 0, v0x5602ec71a9e0_0;  1 drivers
+v0x5602ec6ef0a0_0 .net *"_ivl_1", 0 0, L_0x5602ec71ac40;  1 drivers
+v0x5602ec6eec60_0 .net *"_ivl_11", 0 0, L_0x5602ec71b3c0;  1 drivers
+v0x5602ec6ee3f0_0 .net *"_ivl_13", 0 0, L_0x5602ec71b5f0;  1 drivers
+v0x5602ec6edfc0_0 .net *"_ivl_14", 0 0, L_0x5602ec71b750;  1 drivers
+v0x5602ec719640_0 .net *"_ivl_16", 0 0, L_0x5602ec71b8b0;  1 drivers
+v0x5602ec719720_0 .net *"_ivl_19", 0 0, L_0x5602ec71b920;  1 drivers
+v0x5602ec719800_0 .net *"_ivl_20", 0 0, L_0x5602ec71ba60;  1 drivers
+v0x5602ec7198e0_0 .net *"_ivl_22", 0 0, L_0x5602ec71bb80;  1 drivers
+v0x5602ec7199c0_0 .net *"_ivl_25", 0 0, L_0x5602ec71bbf0;  1 drivers
+v0x5602ec719aa0_0 .net *"_ivl_26", 0 0, L_0x5602ec71bc90;  1 drivers
+v0x5602ec719b80_0 .net *"_ivl_28", 0 0, L_0x5602ec71bdc0;  1 drivers
+v0x5602ec719c60_0 .net *"_ivl_3", 0 0, L_0x5602ec71adc0;  1 drivers
+v0x5602ec719d40_0 .net *"_ivl_31", 0 0, L_0x5602ec71be30;  1 drivers
+v0x5602ec719e20_0 .net *"_ivl_32", 0 0, L_0x5602ec71bf30;  1 drivers
+v0x5602ec719f00_0 .net *"_ivl_34", 0 0, L_0x5602ec71bd50;  1 drivers
+v0x5602ec719fe0_0 .net *"_ivl_38", 0 0, L_0x5602ec71c3e0;  1 drivers
+v0x5602ec71a0c0_0 .net *"_ivl_5", 0 0, L_0x5602ec71af50;  1 drivers
+v0x5602ec71a1a0_0 .net *"_ivl_7", 0 0, L_0x5602ec71b140;  1 drivers
+v0x5602ec71a280_0 .net *"_ivl_9", 0 0, L_0x5602ec71b210;  1 drivers
+v0x5602ec71a360_0 .net "and1", 0 0, L_0x5602ec71b040;  1 drivers
+v0x5602ec71a420_0 .net "and2", 0 0, L_0x5602ec71b300;  1 drivers
+v0x5602ec71a4e0_0 .net "and3", 0 0, L_0x5602ec71b4f0;  1 drivers
+v0x5602ec71a5a0_0 .net "and4", 0 0, L_0x5602ec71b6e0;  1 drivers
+v0x5602ec71a660_0 .net "notA", 0 0, L_0x5602ec71ab70;  1 drivers
+v0x5602ec71a720_0 .net "notB", 0 0, L_0x5602ec71ad30;  1 drivers
+v0x5602ec71a7e0_0 .net "notC", 0 0, L_0x5602ec71aeb0;  1 drivers
+v0x5602ec71a8a0_0 .net "opCode", 7 0, L_0x5602ec71c020;  alias, 1 drivers
+L_0x5602ec71ac40 .part v0x5602ec71a9e0_0, 2, 1;
+L_0x5602ec71adc0 .part v0x5602ec71a9e0_0, 1, 1;
+L_0x5602ec71af50 .part v0x5602ec71a9e0_0, 0, 1;
+L_0x5602ec71b140 .part v0x5602ec71a9e0_0, 2, 1;
+L_0x5602ec71b210 .part v0x5602ec71a9e0_0, 1, 1;
+L_0x5602ec71b3c0 .part v0x5602ec71a9e0_0, 1, 1;
+L_0x5602ec71b5f0 .part v0x5602ec71a9e0_0, 2, 1;
+L_0x5602ec71b920 .part v0x5602ec71a9e0_0, 0, 1;
+L_0x5602ec71bbf0 .part v0x5602ec71a9e0_0, 0, 1;
+L_0x5602ec71be30 .part v0x5602ec71a9e0_0, 0, 1;
+LS_0x5602ec71c020_0_0 .concat8 [ 1 1 1 1], L_0x5602ec71b750, L_0x5602ec71b8b0, L_0x5602ec71ba60, L_0x5602ec71bb80;
+LS_0x5602ec71c020_0_4 .concat8 [ 1 1 1 1], L_0x5602ec71bc90, L_0x5602ec71bdc0, L_0x5602ec71bf30, L_0x5602ec71bd50;
+L_0x5602ec71c020 .concat8 [ 4 4 0 0], LS_0x5602ec71c020_0_0, LS_0x5602ec71c020_0_4;
+L_0x5602ec71c3e0 .part v0x5602ec71a9e0_0, 0, 1;
+    .scope S_0x5602ec702f00;
+T_0 ;
+    %vpi_call 2 13 "$dumpfile", "opCode.vcd" {0 0 0};
+    %vpi_call 2 14 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %pushi/vec4 3, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %pushi/vec4 4, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %pushi/vec4 5, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %pushi/vec4 6, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %pushi/vec4 7, 0, 3;
+    %store/vec4 v0x5602ec71a9e0_0, 0, 3;
+    %delay 3, 0;
+    %vpi_call 2 23 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "opCodeTB.v";
+    "opCode.v";
--- a/verilog/ALU0.2/opCode.v
+++ b/verilog/ALU0.2/opCode.v
@@ -0,0 +1,25 @@
+module opCode (
+    input [2:0] A,
+    output [7:0] opCode
+);
+    wire and1, and2, and3, and4, notA, notB, notC;
+
+    not n1(notA, A[2]);
+    not n2(notB, A[1]);
+    not n3(notC, A[0]);
+
+    and a01(and1, A[2], A[1]);
+    and a02(and2, notA, A[1]);
+    and a03(and3, A[2], notB);
+    and a04(and4, notA, notB);
+
+    and a1(opCode[0], and4, notC);
+    and a2(opCode[1], and4, A[0]);
+    and a3(opCode[2], and2, notC);
+    and a4(opCode[3], and2, A[0]);
+    and a5(opCode[4], and3, notC);
+    and a6(opCode[5], and3, A[0]);
+    and a7(opCode[6], and1, notC);
+    and a8(opCode[7], and1, A[0]);
+
+endmodule
--- a/verilog/ALU0.2/opCode.vcd
+++ b/verilog/ALU0.2/opCode.vcd
@@ -0,0 +1,92 @@
+$date
+	Sun Dec 15 04:12:35 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module opCodeTB $end
+$var wire 8 ! opCode [7:0] $end
+$var reg 3 " A [2:0] $end
+$scope module uut $end
+$var wire 3 # A [2:0] $end
+$var wire 1 $ and1 $end
+$var wire 1 % and2 $end
+$var wire 1 & and3 $end
+$var wire 1 ' and4 $end
+$var wire 1 ( notA $end
+$var wire 1 ) notB $end
+$var wire 1 * notC $end
+$var wire 8 + opCode [7:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b1 +
+1*
+1)
+1(
+1'
+0&
+0%
+0$
+b0 #
+b0 "
+b1 !
+$end
+#3
+0*
+b10 !
+b10 +
+b1 "
+b1 #
+#6
+0'
+0)
+1*
+1%
+b100 !
+b100 +
+b10 "
+b10 #
+#9
+0*
+b1000 !
+b1000 +
+b11 "
+b11 #
+#12
+1&
+0(
+1)
+1*
+0%
+b10000 !
+b10000 +
+b100 "
+b100 #
+#15
+0*
+b100000 !
+b100000 +
+b101 "
+b101 #
+#18
+0&
+0)
+1*
+1$
+b1000000 !
+b1000000 +
+b110 "
+b110 #
+#21
+0*
+b10000000 !
+b10000000 +
+b111 "
+b111 #
+#24
--- a/verilog/ALU0.2/opCode.vcdZone.Identifier
+++ b/verilog/ALU0.2/opCode.vcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/opCode.vZone.Identifier
+++ b/verilog/ALU0.2/opCode.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/opCodeTB.v
+++ b/verilog/ALU0.2/opCodeTB.v
@@ -0,0 +1,26 @@
+module opCodeTB();
+
+reg [2:0] A;
+wire [7:0] opCode;
+
+opCode uut (
+    .A(A),
+
+    .opCode(opCode)
+);
+
+initial begin
+    $dumpfile("opCode.vcd");
+    $dumpvars;
+    A = 3'b000; #3;
+    A = 3'b001; #3;
+    A = 3'b010; #3;
+    A = 3'b011; #3;
+    A = 3'b100; #3;
+    A = 3'b101; #3;
+    A = 3'b110; #3;
+    A = 3'b111; #3;
+    $finish;
+end
+
+endmodule
--- a/verilog/ALU0.2/opCodeTB.vZone.Identifier
+++ b/verilog/ALU0.2/opCodeTB.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/opCodeZone.Identifier
+++ b/verilog/ALU0.2/opCodeZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/selectorTB.v
+++ b/verilog/ALU0.2/selectorTB.v
@@ -0,0 +1,26 @@
+module selectorTB();
+
+reg [3:0] select, A, B;
+reg [7:0] Y;
+reg [2:0] opCodeA;
+wire [7:0] s0;
+
+selector uut (
+    .select(select),
+    .A(A),
+    .B(B),
+    .opCodeA(opCodeA),
+    .s0(s0)
+);
+
+initial begin
+    $dumpfile("selector.vcd");
+    $dumpvars;
+    A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0010; #5;
+    A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0001; #5;
+    A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b0111_0000; select = 4'b0100; #5;
+    A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b0111_0000; select = 4'b1000; #5;
+    $finish;
+end
+
+endmodule
--- a/verilog/ALU0.2/selectorTB.vZone.Identifier
+++ b/verilog/ALU0.2/selectorTB.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/subtraction
+++ b/verilog/ALU0.2/subtraction
@@ -0,0 +1,277 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x56044d0d48c0 .scope module, "subtractionTB" "subtractionTB" 2 1;
+ .timescale 0 0;
+v0x56044d107590_0 .var "A", 3 0;
+v0x56044d107670_0 .var "B", 3 0;
+v0x56044d107740_0 .var "BorrowIN", 0 0;
+v0x56044d107810_0 .net "BorrowOUT", 0 0, L_0x56044d109c20;  1 drivers
+v0x56044d107900_0 .net "Y", 3 0, L_0x56044d10a0c0;  1 drivers
+S_0x56044d0d0e60 .scope module, "uut" "subtraction" 2 9, 3 1 0, S_0x56044d0d48c0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 4 "A";
+    .port_info 1 /INPUT 4 "B";
+    .port_info 2 /INPUT 1 "BorrowIN";
+    .port_info 3 /OUTPUT 4 "Y";
+    .port_info 4 /OUTPUT 1 "BorrowOUT";
+v0x56044d106ef0_0 .net "A", 3 0, v0x56044d107590_0;  1 drivers
+v0x56044d106fd0_0 .net "B", 3 0, v0x56044d107670_0;  1 drivers
+v0x56044d1070b0_0 .net "BorrowIN", 0 0, v0x56044d107740_0;  1 drivers
+v0x56044d1071a0_0 .net "BorrowOUT", 0 0, L_0x56044d109c20;  alias, 1 drivers
+v0x56044d107240_0 .net "Y", 3 0, L_0x56044d10a0c0;  alias, 1 drivers
+o0x7f55d9dc01e8 .functor BUFZ 1, C4<z>; HiZ drive
+; Elide local net with no drivers, v0x56044d107330_0 name=_ivl_39
+v0x56044d107410_0 .net "tempB", 3 0, L_0x56044d10a1d0;  1 drivers
+L_0x56044d107fc0 .part v0x56044d107590_0, 0, 1;
+L_0x56044d108110 .part v0x56044d107670_0, 0, 1;
+L_0x56044d1088f0 .part v0x56044d107590_0, 1, 1;
+L_0x56044d108a20 .part v0x56044d107670_0, 1, 1;
+L_0x56044d108b50 .part L_0x56044d10a1d0, 0, 1;
+L_0x56044d109200 .part v0x56044d107590_0, 2, 1;
+L_0x56044d109400 .part v0x56044d107670_0, 2, 1;
+L_0x56044d1095c0 .part L_0x56044d10a1d0, 1, 1;
+L_0x56044d109cd0 .part v0x56044d107590_0, 3, 1;
+L_0x56044d109e00 .part v0x56044d107670_0, 3, 1;
+L_0x56044d109f90 .part L_0x56044d10a1d0, 2, 1;
+L_0x56044d10a0c0 .concat8 [ 1 1 1 1], L_0x56044d107ca0, L_0x56044d108530, L_0x56044d108e40, L_0x56044d1098f0;
+L_0x56044d10a1d0 .concat [ 1 1 1 1], L_0x56044d107f30, L_0x56044d108860, L_0x56044d109170, o0x7f55d9dc01e8;
+S_0x56044d0deda0 .scope module, "f0" "fullsubtraction" 3 11, 4 1 0, S_0x56044d0d0e60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "BorrowIN";
+    .port_info 3 /OUTPUT 1 "Difference";
+    .port_info 4 /OUTPUT 1 "BorrowOut";
+L_0x56044d107f30 .functor OR 1, L_0x56044d107b90, L_0x56044d107ec0, C4<0>, C4<0>;
+v0x56044d102580_0 .net "A", 0 0, L_0x56044d107fc0;  1 drivers
+v0x56044d102640_0 .net "B", 0 0, L_0x56044d108110;  1 drivers
+v0x56044d102710_0 .net "BorrowIN", 0 0, v0x56044d107740_0;  alias, 1 drivers
+v0x56044d102810_0 .net "BorrowOut", 0 0, L_0x56044d107f30;  1 drivers
+v0x56044d1028b0_0 .net "Difference", 0 0, L_0x56044d107ca0;  1 drivers
+v0x56044d1029a0_0 .net "tempB1", 0 0, L_0x56044d107b90;  1 drivers
+v0x56044d102a70_0 .net "tempB2", 0 0, L_0x56044d107ec0;  1 drivers
+v0x56044d102b40_0 .net "tempD", 0 0, L_0x56044d1079f0;  1 drivers
+S_0x56044d09ecf0 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x56044d0deda0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d1079f0 .functor XOR 1, L_0x56044d107fc0, L_0x56044d108110, C4<0>, C4<0>;
+L_0x56044d107b00 .functor NOT 1, L_0x56044d107fc0, C4<0>, C4<0>, C4<0>;
+L_0x56044d107b90 .functor AND 1, L_0x56044d107b00, L_0x56044d108110, C4<1>, C4<1>;
+v0x56044d0d6940_0 .net "A", 0 0, L_0x56044d107fc0;  alias, 1 drivers
+v0x56044d0d4ef0_0 .net "B", 0 0, L_0x56044d108110;  alias, 1 drivers
+v0x56044d0d3210_0 .net "Borrow", 0 0, L_0x56044d107b90;  alias, 1 drivers
+v0x56044d0d1500_0 .net "Difference", 0 0, L_0x56044d1079f0;  alias, 1 drivers
+v0x56044d0d4c60_0 .net "notA", 0 0, L_0x56044d107b00;  1 drivers
+S_0x56044d102060 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x56044d0deda0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d107ca0 .functor XOR 1, L_0x56044d1079f0, v0x56044d107740_0, C4<0>, C4<0>;
+L_0x56044d107e30 .functor NOT 1, L_0x56044d1079f0, C4<0>, C4<0>, C4<0>;
+L_0x56044d107ec0 .functor AND 1, L_0x56044d107e30, v0x56044d107740_0, C4<1>, C4<1>;
+v0x56044d0d2f80_0 .net "A", 0 0, L_0x56044d1079f0;  alias, 1 drivers
+v0x56044d0d1280_0 .net "B", 0 0, v0x56044d107740_0;  alias, 1 drivers
+v0x56044d102260_0 .net "Borrow", 0 0, L_0x56044d107ec0;  alias, 1 drivers
+v0x56044d102330_0 .net "Difference", 0 0, L_0x56044d107ca0;  alias, 1 drivers
+v0x56044d1023f0_0 .net "notA", 0 0, L_0x56044d107e30;  1 drivers
+S_0x56044d102c30 .scope module, "f1" "fullsubtraction" 3 12, 4 1 0, S_0x56044d0d0e60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "BorrowIN";
+    .port_info 3 /OUTPUT 1 "Difference";
+    .port_info 4 /OUTPUT 1 "BorrowOut";
+L_0x56044d108860 .functor OR 1, L_0x56044d108420, L_0x56044d108750, C4<0>, C4<0>;
+v0x56044d103b70_0 .net "A", 0 0, L_0x56044d1088f0;  1 drivers
+v0x56044d103c30_0 .net "B", 0 0, L_0x56044d108a20;  1 drivers
+v0x56044d103d00_0 .net "BorrowIN", 0 0, L_0x56044d108b50;  1 drivers
+v0x56044d103e00_0 .net "BorrowOut", 0 0, L_0x56044d108860;  1 drivers
+v0x56044d103ea0_0 .net "Difference", 0 0, L_0x56044d108530;  1 drivers
+v0x56044d103f90_0 .net "tempB1", 0 0, L_0x56044d108420;  1 drivers
+v0x56044d104060_0 .net "tempB2", 0 0, L_0x56044d108750;  1 drivers
+v0x56044d104130_0 .net "tempD", 0 0, L_0x56044d108240;  1 drivers
+S_0x56044d102e10 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x56044d102c30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d108240 .functor XOR 1, L_0x56044d1088f0, L_0x56044d108a20, C4<0>, C4<0>;
+L_0x56044d108390 .functor NOT 1, L_0x56044d1088f0, C4<0>, C4<0>, C4<0>;
+L_0x56044d108420 .functor AND 1, L_0x56044d108390, L_0x56044d108a20, C4<1>, C4<1>;
+v0x56044d103020_0 .net "A", 0 0, L_0x56044d1088f0;  alias, 1 drivers
+v0x56044d103100_0 .net "B", 0 0, L_0x56044d108a20;  alias, 1 drivers
+v0x56044d1031c0_0 .net "Borrow", 0 0, L_0x56044d108420;  alias, 1 drivers
+v0x56044d103290_0 .net "Difference", 0 0, L_0x56044d108240;  alias, 1 drivers
+v0x56044d103350_0 .net "notA", 0 0, L_0x56044d108390;  1 drivers
+S_0x56044d1034e0 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x56044d102c30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d108530 .functor XOR 1, L_0x56044d108240, L_0x56044d108b50, C4<0>, C4<0>;
+L_0x56044d1086c0 .functor NOT 1, L_0x56044d108240, C4<0>, C4<0>, C4<0>;
+L_0x56044d108750 .functor AND 1, L_0x56044d1086c0, L_0x56044d108b50, C4<1>, C4<1>;
+v0x56044d1036e0_0 .net "A", 0 0, L_0x56044d108240;  alias, 1 drivers
+v0x56044d1037b0_0 .net "B", 0 0, L_0x56044d108b50;  alias, 1 drivers
+v0x56044d103850_0 .net "Borrow", 0 0, L_0x56044d108750;  alias, 1 drivers
+v0x56044d103920_0 .net "Difference", 0 0, L_0x56044d108530;  alias, 1 drivers
+v0x56044d1039e0_0 .net "notA", 0 0, L_0x56044d1086c0;  1 drivers
+S_0x56044d104220 .scope module, "f2" "fullsubtraction" 3 13, 4 1 0, S_0x56044d0d0e60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "BorrowIN";
+    .port_info 3 /OUTPUT 1 "Difference";
+    .port_info 4 /OUTPUT 1 "BorrowOut";
+L_0x56044d109170 .functor OR 1, L_0x56044d108d80, L_0x56044d109060, C4<0>, C4<0>;
+v0x56044d105170_0 .net "A", 0 0, L_0x56044d109200;  1 drivers
+v0x56044d105230_0 .net "B", 0 0, L_0x56044d109400;  1 drivers
+v0x56044d105300_0 .net "BorrowIN", 0 0, L_0x56044d1095c0;  1 drivers
+v0x56044d105400_0 .net "BorrowOut", 0 0, L_0x56044d109170;  1 drivers
+v0x56044d1054a0_0 .net "Difference", 0 0, L_0x56044d108e40;  1 drivers
+v0x56044d105590_0 .net "tempB1", 0 0, L_0x56044d108d80;  1 drivers
+v0x56044d105660_0 .net "tempB2", 0 0, L_0x56044d109060;  1 drivers
+v0x56044d105730_0 .net "tempD", 0 0, L_0x56044d108c80;  1 drivers
+S_0x56044d104430 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x56044d104220;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d108c80 .functor XOR 1, L_0x56044d109200, L_0x56044d109400, C4<0>, C4<0>;
+L_0x56044d108cf0 .functor NOT 1, L_0x56044d109200, C4<0>, C4<0>, C4<0>;
+L_0x56044d108d80 .functor AND 1, L_0x56044d108cf0, L_0x56044d109400, C4<1>, C4<1>;
+v0x56044d104640_0 .net "A", 0 0, L_0x56044d109200;  alias, 1 drivers
+v0x56044d104700_0 .net "B", 0 0, L_0x56044d109400;  alias, 1 drivers
+v0x56044d1047c0_0 .net "Borrow", 0 0, L_0x56044d108d80;  alias, 1 drivers
+v0x56044d104890_0 .net "Difference", 0 0, L_0x56044d108c80;  alias, 1 drivers
+v0x56044d104950_0 .net "notA", 0 0, L_0x56044d108cf0;  1 drivers
+S_0x56044d104ae0 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x56044d104220;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d108e40 .functor XOR 1, L_0x56044d108c80, L_0x56044d1095c0, C4<0>, C4<0>;
+L_0x56044d108fd0 .functor NOT 1, L_0x56044d108c80, C4<0>, C4<0>, C4<0>;
+L_0x56044d109060 .functor AND 1, L_0x56044d108fd0, L_0x56044d1095c0, C4<1>, C4<1>;
+v0x56044d104ce0_0 .net "A", 0 0, L_0x56044d108c80;  alias, 1 drivers
+v0x56044d104db0_0 .net "B", 0 0, L_0x56044d1095c0;  alias, 1 drivers
+v0x56044d104e50_0 .net "Borrow", 0 0, L_0x56044d109060;  alias, 1 drivers
+v0x56044d104f20_0 .net "Difference", 0 0, L_0x56044d108e40;  alias, 1 drivers
+v0x56044d104fe0_0 .net "notA", 0 0, L_0x56044d108fd0;  1 drivers
+S_0x56044d105820 .scope module, "f3" "fullsubtraction" 3 14, 4 1 0, S_0x56044d0d0e60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "BorrowIN";
+    .port_info 3 /OUTPUT 1 "Difference";
+    .port_info 4 /OUTPUT 1 "BorrowOut";
+L_0x56044d109c20 .functor OR 1, L_0x56044d109880, L_0x56044d109b10, C4<0>, C4<0>;
+v0x56044d106840_0 .net "A", 0 0, L_0x56044d109cd0;  1 drivers
+v0x56044d106900_0 .net "B", 0 0, L_0x56044d109e00;  1 drivers
+v0x56044d1069d0_0 .net "BorrowIN", 0 0, L_0x56044d109f90;  1 drivers
+v0x56044d106ad0_0 .net "BorrowOut", 0 0, L_0x56044d109c20;  alias, 1 drivers
+v0x56044d106b70_0 .net "Difference", 0 0, L_0x56044d1098f0;  1 drivers
+v0x56044d106c60_0 .net "tempB1", 0 0, L_0x56044d109880;  1 drivers
+v0x56044d106d30_0 .net "tempB2", 0 0, L_0x56044d109b10;  1 drivers
+v0x56044d106e00_0 .net "tempD", 0 0, L_0x56044d109740;  1 drivers
+S_0x56044d105a00 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x56044d105820;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d109740 .functor XOR 1, L_0x56044d109cd0, L_0x56044d109e00, C4<0>, C4<0>;
+L_0x56044d1097f0 .functor NOT 1, L_0x56044d109cd0, C4<0>, C4<0>, C4<0>;
+L_0x56044d109880 .functor AND 1, L_0x56044d1097f0, L_0x56044d109e00, C4<1>, C4<1>;
+v0x56044d105c80_0 .net "A", 0 0, L_0x56044d109cd0;  alias, 1 drivers
+v0x56044d105d60_0 .net "B", 0 0, L_0x56044d109e00;  alias, 1 drivers
+v0x56044d105e20_0 .net "Borrow", 0 0, L_0x56044d109880;  alias, 1 drivers
+v0x56044d105ef0_0 .net "Difference", 0 0, L_0x56044d109740;  alias, 1 drivers
+v0x56044d105fb0_0 .net "notA", 0 0, L_0x56044d1097f0;  1 drivers
+S_0x56044d106140 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x56044d105820;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "Difference";
+    .port_info 3 /OUTPUT 1 "Borrow";
+L_0x56044d1098f0 .functor XOR 1, L_0x56044d109740, L_0x56044d109f90, C4<0>, C4<0>;
+L_0x56044d109a80 .functor NOT 1, L_0x56044d109740, C4<0>, C4<0>, C4<0>;
+L_0x56044d109b10 .functor AND 1, L_0x56044d109a80, L_0x56044d109f90, C4<1>, C4<1>;
+v0x56044d1063b0_0 .net "A", 0 0, L_0x56044d109740;  alias, 1 drivers
+v0x56044d106480_0 .net "B", 0 0, L_0x56044d109f90;  alias, 1 drivers
+v0x56044d106520_0 .net "Borrow", 0 0, L_0x56044d109b10;  alias, 1 drivers
+v0x56044d1065f0_0 .net "Difference", 0 0, L_0x56044d1098f0;  alias, 1 drivers
+v0x56044d1066b0_0 .net "notA", 0 0, L_0x56044d109a80;  1 drivers
+    .scope S_0x56044d0d48c0;
+T_0 ;
+    %vpi_call 2 18 "$dumpfile", "subtraction.vcd" {0 0 0};
+    %vpi_call 2 19 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56044d107590_0, 0, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56044d107670_0, 0, 4;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56044d107740_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 6, 0, 4;
+    %store/vec4 v0x56044d107590_0, 0, 4;
+    %pushi/vec4 2, 0, 4;
+    %store/vec4 v0x56044d107670_0, 0, 4;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56044d107740_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 2, 0, 4;
+    %store/vec4 v0x56044d107590_0, 0, 4;
+    %pushi/vec4 6, 0, 4;
+    %store/vec4 v0x56044d107670_0, 0, 4;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56044d107740_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 12, 0, 4;
+    %store/vec4 v0x56044d107590_0, 0, 4;
+    %pushi/vec4 4, 0, 4;
+    %store/vec4 v0x56044d107670_0, 0, 4;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56044d107740_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 8, 0, 4;
+    %store/vec4 v0x56044d107590_0, 0, 4;
+    %pushi/vec4 8, 0, 4;
+    %store/vec4 v0x56044d107670_0, 0, 4;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56044d107740_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x56044d107590_0, 0, 4;
+    %pushi/vec4 1, 0, 4;
+    %store/vec4 v0x56044d107670_0, 0, 4;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x56044d107740_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 33 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 6;
+    "N/A";
+    "<interactive>";
+    "subtractionTB.v";
+    "subtraction.v";
+    "fullsubtraction.v";
+    "halfsubtraction.v";
--- a/verilog/ALU0.2/subtraction.v
+++ b/verilog/ALU0.2/subtraction.v
@@ -0,0 +1,16 @@
+module subtraction (
+    input [3:0] A, B,
+    input BorrowIN,
+    output [3:0] Y,
+    output BorrowOUT //Overflow signal'ini yani negatif gonderecek
+);
+
+wire [3:0] tempB;
+
+// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
+fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
+fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
+fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
+fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
+
+endmodule
--- a/verilog/ALU0.2/subtraction.vcd
+++ b/verilog/ALU0.2/subtraction.vcd
@@ -0,0 +1,274 @@
+$date
+	Wed Dec 25 00:48:05 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module subtractionTB $end
+$var wire 4 ! Y [3:0] $end
+$var wire 1 " BorrowOUT $end
+$var reg 4 # A [3:0] $end
+$var reg 4 $ B [3:0] $end
+$var reg 1 % BorrowIN $end
+$scope module uut $end
+$var wire 4 & A [3:0] $end
+$var wire 4 ' B [3:0] $end
+$var wire 1 % BorrowIN $end
+$var wire 4 ( tempB [3:0] $end
+$var wire 4 ) Y [3:0] $end
+$var wire 1 " BorrowOUT $end
+$scope module f0 $end
+$var wire 1 * A $end
+$var wire 1 + B $end
+$var wire 1 % BorrowIN $end
+$var wire 1 , BorrowOut $end
+$var wire 1 - tempD $end
+$var wire 1 . tempB2 $end
+$var wire 1 / tempB1 $end
+$var wire 1 0 Difference $end
+$scope module hf1 $end
+$var wire 1 * A $end
+$var wire 1 + B $end
+$var wire 1 / Borrow $end
+$var wire 1 - Difference $end
+$var wire 1 1 notA $end
+$upscope $end
+$scope module hf2 $end
+$var wire 1 - A $end
+$var wire 1 % B $end
+$var wire 1 . Borrow $end
+$var wire 1 0 Difference $end
+$var wire 1 2 notA $end
+$upscope $end
+$upscope $end
+$scope module f1 $end
+$var wire 1 3 A $end
+$var wire 1 4 B $end
+$var wire 1 5 BorrowIN $end
+$var wire 1 6 BorrowOut $end
+$var wire 1 7 tempD $end
+$var wire 1 8 tempB2 $end
+$var wire 1 9 tempB1 $end
+$var wire 1 : Difference $end
+$scope module hf1 $end
+$var wire 1 3 A $end
+$var wire 1 4 B $end
+$var wire 1 9 Borrow $end
+$var wire 1 7 Difference $end
+$var wire 1 ; notA $end
+$upscope $end
+$scope module hf2 $end
+$var wire 1 7 A $end
+$var wire 1 5 B $end
+$var wire 1 8 Borrow $end
+$var wire 1 : Difference $end
+$var wire 1 < notA $end
+$upscope $end
+$upscope $end
+$scope module f2 $end
+$var wire 1 = A $end
+$var wire 1 > B $end
+$var wire 1 ? BorrowIN $end
+$var wire 1 @ BorrowOut $end
+$var wire 1 A tempD $end
+$var wire 1 B tempB2 $end
+$var wire 1 C tempB1 $end
+$var wire 1 D Difference $end
+$scope module hf1 $end
+$var wire 1 = A $end
+$var wire 1 > B $end
+$var wire 1 C Borrow $end
+$var wire 1 A Difference $end
+$var wire 1 E notA $end
+$upscope $end
+$scope module hf2 $end
+$var wire 1 A A $end
+$var wire 1 ? B $end
+$var wire 1 B Borrow $end
+$var wire 1 D Difference $end
+$var wire 1 F notA $end
+$upscope $end
+$upscope $end
+$scope module f3 $end
+$var wire 1 G A $end
+$var wire 1 H B $end
+$var wire 1 I BorrowIN $end
+$var wire 1 " BorrowOut $end
+$var wire 1 J tempD $end
+$var wire 1 K tempB2 $end
+$var wire 1 L tempB1 $end
+$var wire 1 M Difference $end
+$scope module hf1 $end
+$var wire 1 G A $end
+$var wire 1 H B $end
+$var wire 1 L Borrow $end
+$var wire 1 J Difference $end
+$var wire 1 N notA $end
+$upscope $end
+$scope module hf2 $end
+$var wire 1 J A $end
+$var wire 1 I B $end
+$var wire 1 K Borrow $end
+$var wire 1 M Difference $end
+$var wire 1 O notA $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+1O
+1N
+0M
+0L
+0K
+0J
+0I
+0H
+0G
+1F
+1E
+0D
+0C
+0B
+0A
+0@
+0?
+0>
+0=
+1<
+1;
+0:
+09
+08
+07
+06
+05
+04
+03
+12
+11
+00
+0/
+0.
+0-
+0,
+0+
+0*
+b0 )
+bz000 (
+b0 '
+b0 &
+0%
+b0 $
+b0 #
+0"
+b0 !
+$end
+#10
+b100 !
+b100 )
+1D
+0F
+0;
+1A
+0E
+14
+13
+1=
+b10 $
+b10 '
+b110 #
+b110 &
+#20
+1"
+b1100 !
+b1100 )
+1M
+1K
+1I
+bz100 (
+1@
+1C
+1E
+1>
+0=
+b110 $
+b110 '
+b10 #
+b10 &
+#30
+0I
+0"
+bz000 (
+0@
+0K
+0D
+1F
+0C
+b1000 !
+b1000 )
+1M
+0O
+1;
+0A
+0E
+1J
+0N
+04
+03
+1=
+1G
+b100 $
+b100 '
+b1100 #
+b1100 &
+#40
+b0 !
+b0 )
+0M
+1O
+0J
+1E
+0>
+1H
+0=
+b1000 $
+b1000 '
+b1000 #
+b1000 &
+#50
+15
+1M
+0O
+0:
+0<
+1D
+0F
+bz001 (
+1,
+1J
+01
+17
+0;
+1A
+0E
+b1101 !
+b1101 )
+10
+1.
+1+
+0H
+1*
+13
+1=
+1%
+b1 $
+b1 '
+b1111 #
+b1111 &
+#60
--- a/verilog/ALU0.2/subtraction.vcdZone.Identifier
+++ b/verilog/ALU0.2/subtraction.vcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/subtraction.vZone.Identifier
+++ b/verilog/ALU0.2/subtraction.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/subtractionTB.v
+++ b/verilog/ALU0.2/subtractionTB.v
@@ -0,0 +1,41 @@
+module subtractionTB;
+
+reg [3:0] A, B;
+reg BorrowIN;
+wire [3:0] Y;
+wire BorrowOUT;
+
+// Instantiate the subtraction module
+subtraction uut (
+    .A(A),
+    .B(B),
+    .BorrowIN(BorrowIN),
+    .Y(Y),
+    .BorrowOUT(BorrowOUT)
+);
+
+initial begin
+    $dumpfile("subtraction.vcd");
+    $dumpvars;
+    // Initialize inputs
+    A = 4'b0000;  // Set A to 0
+    B = 4'b0000;  // Set B to 0
+    BorrowIN = 0;  // No borrow input
+
+    // Apply test cases
+    #10 A = 4'b0110; B = 4'b0010; BorrowIN = 0; // A = 6, B = 2
+    #10 A = 4'b0010; B = 4'b0110; BorrowIN = 0; // A = 2, B = 6
+    #10 A = 4'b1100; B = 4'b0100; BorrowIN = 0; // A = -4, B = 4
+    #10 A = 4'b1000; B = 4'b1000; BorrowIN = 0; // A = -8, B = -8
+    #10 A = 4'b1111; B = 4'b0001; BorrowIN = 1; // A = -1, B = 1, with borrow input
+    
+    // Wait for the results
+    #10 $finish;
+end
+
+//initial begin
+    // Monitor the values of Y and overflow
+  //  $monitor("At time %t: A = %b, B = %b, Y = %b, BorrowOut = %b, overflow = %b", $time, A, B, Y, BorrowOut, overflow);
+//end
+
+endmodule
--- a/verilog/ALU0.2/subtractionTB.vZone.Identifier
+++ b/verilog/ALU0.2/subtractionTB.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALU0.2/subtractionZone.Identifier
+++ b/verilog/ALU0.2/subtractionZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/ALU
+++ b/verilog/ALUTangTest/ALU
--- a/verilog/ALUTangTest/ALU.v
+++ b/verilog/ALUTangTest/ALU.v
@@ -0,0 +1,79 @@
+module ALU (
+    input [3:0] A, B,
+    input CarryIN,
+    input [2:0] opCodeA,
+    output [11:0] bcd,
+    output CarryOUT, overflow
+);
+
+// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
+
+wire [7:0] opCode8;
+wire [3:0] add_Y, sub_Y;
+wire [3:0] resultA, resultO, resultX, lUOutput1;
+wire [3:0] aUtemp1, aUtemp2, lUOutput2;
+wire [3:0] wireY, wireLA;
+wire [7:0] opwireM, wireM, Y;
+
+opCode opCd (.A(opCodeA), .opCode(opCode8));
+
+arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
+logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
+multiplier mU (.A(A), .B(B), .Y(opwireM));
+
+or o01 (lUOutput1[0], resultA[0], resultO[0]);
+or o02 (lUOutput1[1], resultA[1], resultO[1]);
+or o03 (lUOutput1[2], resultA[2], resultO[2]);
+or o04 (lUOutput1[3], resultA[3], resultO[3]);
+
+or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
+or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
+or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
+or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
+
+
+and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
+and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
+and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
+and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
+
+
+and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
+and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
+and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
+and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
+
+and a21 (wireM[0], opCode8[2], opwireM[0]);
+and a22 (wireM[1], opCode8[2], opwireM[1]);
+and a23 (wireM[2], opCode8[2], opwireM[2]);
+and a24 (wireM[3], opCode8[2], opwireM[3]);
+and a25 (wireM[4], opCode8[2], opwireM[4]);
+and a26 (wireM[5], opCode8[2], opwireM[5]);
+and a27 (wireM[6], opCode8[2], opwireM[6]);
+and a28 (wireM[7], opCode8[2], opwireM[7]);
+
+
+or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
+or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
+or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
+or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
+
+
+or o1 (wireLA[0], lUOutput2[0], wireY[0]);
+or o2 (wireLA[1], lUOutput2[1], wireY[1]);
+or o3 (wireLA[2], lUOutput2[2], wireY[2]);
+or o4 (wireLA[3], lUOutput2[3], wireY[3]);
+
+or o31 (Y[0], wireLA[0], wireM[0]);
+or o32 (Y[1], wireLA[1], wireM[1]);
+or o33 (Y[2], wireLA[2], wireM[2]);
+or o34 (Y[3], wireLA[3], wireM[3]);
+or o35 (Y[4], 1'b0, wireM[4]);
+or o36 (Y[5], 1'b0, wireM[5]);
+or o37 (Y[6], 1'b0, wireM[6]);
+or o38 (Y[7], 1'b0, wireM[7]);
+
+BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
+
+
+endmodule
--- a/verilog/ALUTangTest/ALU.vcd
+++ b/verilog/ALUTangTest/ALU.vcd
--- a/verilog/ALUTangTest/ALU.vcdZone.Identifier
+++ b/verilog/ALUTangTest/ALU.vcdZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/ALU.vZone.Identifier
+++ b/verilog/ALUTangTest/ALU.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/ALUtb.v
+++ b/verilog/ALUTangTest/ALUtb.v
@@ -0,0 +1,26 @@
+module ALUtb();
+
+reg [3:0] A,B;
+reg CarryIN;
+reg [2:0] opCodeA;
+wire CarryOUT, overflow;
+wire [7:0] Y;
+
+ALU uut (
+    .A(A),
+    .B(B),
+    .CarryIN(CarryIN),
+    .opCodeA(opCodeA),
+    .CarryOUT(CarryOUT),
+    .overflow(overflow),
+    .Y(Y)
+);
+
+initial begin
+    $dumpfile("ALU.vcd");
+    $dumpvars;
+    A = 4'b1111; B = 4'b0001; CarryIN = 1'b0; opCodeA = 3'b001; #5;
+    $finish;
+end
+
+endmodule
--- a/verilog/ALUTangTest/ALUtb.vZone.Identifier
+++ b/verilog/ALUTangTest/ALUtb.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/ALUZone.Identifier
+++ b/verilog/ALUTangTest/ALUZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/BinaryToBCD.v
+++ b/verilog/ALUTangTest/BinaryToBCD.v
@@ -0,0 +1,79 @@
+module BinaryToBCD (
+    input [7:0] binary,
+    output [11:0] bcd
+);
+
+wire empty1, empty2;
+wire [3:0] dab1, dab2, dab3, dab4, dab5;
+
+and a111 (empty1, 1'b0, 1'b0);
+and a000 (empty2, 1'b0, 1'b0);
+and a222 (bcd[11], 1'b0, 1'b0);
+and a223 (bcd[10], 1'b0, 1'b0);
+
+dabble d1t (.A((empty1)),
+.B(binary[7]),
+.C(binary[6]),
+.D(binary[5]),
+.X(dab1[0]),
+.Y(dab1[1]),
+.Z(dab1[2]),
+.E(dab1[3]));
+
+dabble d2u (.A((dab1[1])),
+.B(dab1[2]),
+.C(dab1[3]),
+.D(binary[4]),
+.X(dab2[0]),
+.Y(dab2[1]),
+.Z(dab2[2]),
+.E(dab2[3]));
+
+dabble d3v (.A((dab2[1])),
+.B(dab2[2]),
+.C(dab2[3]),
+.D(binary[3]),
+.X(dab3[0]),
+.Y(dab3[1]),
+.Z(dab3[2]),
+.E(dab3[3]));
+
+dabble d4w (.A((empty2)),
+.B(dab1[0]),
+.C(dab2[0]),
+.D(dab3[0]),
+.X(bcd[9]),
+.Y(dab4[1]),
+.Z(dab4[2]),
+.E(dab4[3]));
+
+dabble d5x (.A((dab3[1])),
+.B(dab3[2]),
+.C(dab3[3]),
+.D(binary[2]),
+.X(dab5[0]),
+.Y(dab5[1]),
+.Z(dab5[2]),
+.E(dab5[3]));
+
+dabble d6y (.A((dab4[1])),
+.B(dab4[2]),
+.C(dab4[3]),
+.D(dab5[0]),
+.X(bcd[8]),
+.Y(bcd[7]),
+.Z(bcd[6]),
+.E(bcd[5]));
+
+dabble d7z (.A((dab5[1])),
+.B(dab5[2]),
+.C(dab5[3]),
+.D(binary[1]),
+.X(bcd[4]),
+.Y(bcd[3]),
+.Z(bcd[2]),
+.E(bcd[1]));
+
+or o1 (bcd[0], binary[0], 1'b0);
+
+endmodule
--- a/verilog/ALUTangTest/BinaryToBCD.vZone.Identifier
+++ b/verilog/ALUTangTest/BinaryToBCD.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/addition.v
+++ b/verilog/ALUTangTest/addition.v
@@ -0,0 +1,20 @@
+module addition (
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [2:0] Carry4;
+
+fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
+fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
+fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
+fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
+
+
+//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
+xor ov1 (overflow, Carry4[2], CarryOUT);
+
+endmodule
--- a/verilog/ALUTangTest/addition.vZone.Identifier
+++ b/verilog/ALUTangTest/addition.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/arithmeticUnit.v
+++ b/verilog/ALUTangTest/arithmeticUnit.v
@@ -0,0 +1,33 @@
+module arithmeticUnit (
+    input [1:0] opCode,
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] add_Y, sub_Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [3:0] addY, subY;
+wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
+
+addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
+subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
+
+and add1 (add_Y[0], opCode[0], addY[0]);
+and add2 (add_Y[1], opCode[0], addY[1]);
+and add3 (add_Y[2], opCode[0], addY[2]);
+and add4 (add_Y[3], opCode[0], addY[3]);
+
+and sub1 (sub_Y[0], opCode[1], subY[0]);
+and sub2 (sub_Y[1], opCode[1], subY[1]);
+and sub3 (sub_Y[2], opCode[1], subY[2]);
+and sub4 (sub_Y[3], opCode[1], subY[3]);
+
+// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
+and and10 (tempCSub, CarryOUTSUB, opCode[1]);
+and and11 (tempCAdd, CarryOUTADD, opCode[0]);
+or or4 (CarryOUT, tempCAdd, tempCSub);
+
+and add12 (overflow, opCode[0], tempoverflow);
+
+endmodule
--- a/verilog/ALUTangTest/arithmeticUnit.vZone.Identifier
+++ b/verilog/ALUTangTest/arithmeticUnit.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/compile.sh
+++ b/verilog/ALUTangTest/compile.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+# Granting execute permissions to this script (one-time setup)
+# chmod +x script_name.sh
+
+# Using Icarus Verilog to compile Verilog files for simulation
+iverilog -o top top.v topTB.v ALU.v selector.v BinaryToBCD.v arithmeticUnit.v logicUnit.v multiplier.v opCode.v addition.v dabble.v subtraction.v fulladder.v fullsubtraction.v halfadder.v halfsubtraction.v
+
+# Running the simulation
+vvp top
--- a/verilog/ALUTangTest/compile.shZone.Identifier
+++ b/verilog/ALUTangTest/compile.shZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/dabble.v
+++ b/verilog/ALUTangTest/dabble.v
@@ -0,0 +1,22 @@
+module dabble (
+    input A, B, C, D,
+    output X, Y, Z, E
+);
+
+wire xor1, nor1, xor2, nor2, nor3, or1;
+
+xor xo1 (xor1, A, D);
+nor no1 (nor1, A, B);
+xor xo2 (xor2, A, C);
+
+nor no2 (nor2, xor1, xor2);
+
+nor no3 (nor3, nor2, nor1);
+buf bu1 (X, nor3);
+or o1 (or1, xor1, nor1);
+
+nor no4 (Y, or1, C);
+and an1 (Z, or1, xor2);
+xor xo3 (E, nor3, D);
+
+endmodule
--- a/verilog/ALUTangTest/dabble.vZone.Identifier
+++ b/verilog/ALUTangTest/dabble.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/fulladder.v
+++ b/verilog/ALUTangTest/fulladder.v
@@ -0,0 +1,12 @@
+module fulladder (
+    input A, B, Carry,
+    output Sum, CarryO
+);
+
+wire xor1, and1, and2;
+
+halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
+halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
+or o1 (CarryO, and1, and2);
+
+endmodule
--- a/verilog/ALUTangTest/fulladder.vZone.Identifier
+++ b/verilog/ALUTangTest/fulladder.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/fullsubtraction.v
+++ b/verilog/ALUTangTest/fullsubtraction.v
@@ -0,0 +1,12 @@
+module fullsubtraction (
+    input A, B, BorrowIN,
+    output Difference, BorrowOut
+);
+
+wire tempD, tempB1, tempB2;
+
+halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
+halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
+or o1 (BorrowOut, tempB1, tempB2);
+
+endmodule
--- a/verilog/ALUTangTest/fullsubtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/fullsubtraction.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/halfadder.v
+++ b/verilog/ALUTangTest/halfadder.v
@@ -0,0 +1,9 @@
+module halfadder (
+    input A, B,
+    output Sum, Carry
+);
+
+and a1 (Carry, A, B);
+xor xo1 (Sum, A, B);
+
+endmodule
--- a/verilog/ALUTangTest/halfadder.vZone.Identifier
+++ b/verilog/ALUTangTest/halfadder.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/halfsubtraction.v
+++ b/verilog/ALUTangTest/halfsubtraction.v
@@ -0,0 +1,12 @@
+module halfsubtraction (
+    input A, B,
+    output Difference, Borrow
+);
+
+wire notA;
+
+xor xo1 (Difference, A, B);
+not a1 (notA, A);
+and an1 (Borrow, notA, B);
+
+endmodule
--- a/verilog/ALUTangTest/halfsubtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/halfsubtraction.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/verilog/ALUTangTest/logicUnit.v
+++ b/verilog/ALUTangTest/logicUnit.v
@@ -0,0 +1,39 @@
+module logicUnit (
+    input [2:0] opCode,
+    input [3:0] A, B,
+    output [3:0] resultA, resultO, resultX
+);
+
+wire [3:0] and1, or1, xor1;
+
+and a01 (and1[0], A[0], B[0]);
+and a02 (and1[1], A[1], B[1]);
+and a03 (and1[2], A[2], B[2]);
+and a04 (and1[3], A[3], B[3]);
+
+or o01 (or1[0], A[0], B[0]);
+or o02 (or1[1], A[1], B[1]);
+or o03 (or1[2], A[2], B[2]);
+or o04 (or1[3], A[3], B[3]);
+
+xor xor01 (xor1[0], A[0], B[0]);
+xor xor02 (xor1[1], A[1], B[1]);
+xor xor03 (xor1[2], A[2], B[2]);
+xor xor04 (xor1[3], A[3], B[3]);
+
+and a_o1 (resultA[0], opCode[0], and1[0]);
+and a_o2 (resultA[1], opCode[0], and1[1]);
+and a_o3 (resultA[2], opCode[0], and1[2]);
+and a_o4 (resultA[3], opCode[0], and1[3]);
+
+and o_o1 (resultO[0], opCode[1], or1[0]);
+and o_o2 (resultO[1], opCode[1], or1[1]);
+and o_o3 (resultO[2], opCode[1], or1[2]);
+and o_o4 (resultO[3], opCode[1], or1[3]);
+
+and x_o1 (resultX[0], opCode[2], xor1[0]);
+and x_o2 (resultX[1], opCode[2], xor1[1]);
+and x_o3 (resultX[2], opCode[2], xor1[2]);
+and x_o4 (resultX[3], opCode[2], xor1[3]);
+
+endmodule
--- a/verilog/ALUTangTest/logicUnit.vZone.Identifier
+++ b/verilog/ALUTangTest/logicUnit.vZone.Identifier
@@ -0,0 +1,2 @@
+[ZoneTransfer]
+ZoneId=3
--- a/Show More
+++ b/Show More