initial commit

2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
--- a/gowin/ALU/src/ALU.v
+++ b/gowin/ALU/src/ALU.v
@ -0,0 +1,79 @@
+module ALU (
+    input [3:0] A, B,
+    input CarryIN,
+    input [2:0] opCodeA,
+    output [11:0] bcd,
+    output CarryOUT, overflow
+);
+
+// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
+
+wire [7:0] opCode8;
+wire [3:0] add_Y, sub_Y;
+wire [3:0] resultA, resultO, resultX, lUOutput1;
+wire [3:0] aUtemp1, aUtemp2, lUOutput2;
+wire [3:0] wireY, wireLA;
+wire [7:0] opwireM, wireM, Y;
+
+opCode opCd (.A(opCodeA), .opCode(opCode8));
+
+arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
+logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
+multiplier mU (.A(A), .B(B), .Y(opwireM));
+
+or o01 (lUOutput1[0], resultA[0], resultO[0]);
+or o02 (lUOutput1[1], resultA[1], resultO[1]);
+or o03 (lUOutput1[2], resultA[2], resultO[2]);
+or o04 (lUOutput1[3], resultA[3], resultO[3]);
+
+or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
+or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
+or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
+or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
+
+
+and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
+and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
+and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
+and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
+
+
+and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
+and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
+and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
+and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
+
+and a21 (wireM[0], opCode8[2], opwireM[0]);
+and a22 (wireM[1], opCode8[2], opwireM[1]);
+and a23 (wireM[2], opCode8[2], opwireM[2]);
+and a24 (wireM[3], opCode8[2], opwireM[3]);
+and a25 (wireM[4], opCode8[2], opwireM[4]);
+and a26 (wireM[5], opCode8[2], opwireM[5]);
+and a27 (wireM[6], opCode8[2], opwireM[6]);
+and a28 (wireM[7], opCode8[2], opwireM[7]);
+
+
+or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
+or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
+or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
+or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
+
+
+or o1 (wireLA[0], lUOutput2[0], wireY[0]);
+or o2 (wireLA[1], lUOutput2[1], wireY[1]);
+or o3 (wireLA[2], lUOutput2[2], wireY[2]);
+or o4 (wireLA[3], lUOutput2[3], wireY[3]);
+
+or o31 (Y[0], wireLA[0], wireM[0]);
+or o32 (Y[1], wireLA[1], wireM[1]);
+or o33 (Y[2], wireLA[2], wireM[2]);
+or o34 (Y[3], wireLA[3], wireM[3]);
+or o35 (Y[4], 1'b0, wireM[4]);
+or o36 (Y[5], 1'b0, wireM[5]);
+or o37 (Y[6], 1'b0, wireM[6]);
+or o38 (Y[7], 1'b0, wireM[7]);
+
+BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
+
+
+endmodule
--- a/gowin/ALU/src/BinaryToBCD.v
+++ b/gowin/ALU/src/BinaryToBCD.v
@ -0,0 +1,79 @@
+module BinaryToBCD (
+    input [7:0] binary,
+    output [11:0] bcd
+);
+
+wire empty1, empty2;
+wire [3:0] dab1, dab2, dab3, dab4, dab5;
+
+and a111 (empty1, 1'b0, 1'b0);
+and a000 (empty2, 1'b0, 1'b0);
+and a222 (bcd[11], 1'b0, 1'b0);
+and a223 (bcd[10], 1'b0, 1'b0);
+
+dabble d1t (.A((empty1)),
+.B(binary[7]),
+.C(binary[6]),
+.D(binary[5]),
+.X(dab1[0]),
+.Y(dab1[1]),
+.Z(dab1[2]),
+.E(dab1[3]));
+
+dabble d2u (.A((dab1[1])),
+.B(dab1[2]),
+.C(dab1[3]),
+.D(binary[4]),
+.X(dab2[0]),
+.Y(dab2[1]),
+.Z(dab2[2]),
+.E(dab2[3]));
+
+dabble d3v (.A((dab2[1])),
+.B(dab2[2]),
+.C(dab2[3]),
+.D(binary[3]),
+.X(dab3[0]),
+.Y(dab3[1]),
+.Z(dab3[2]),
+.E(dab3[3]));
+
+dabble d4w (.A((empty2)),
+.B(dab1[0]),
+.C(dab2[0]),
+.D(dab3[0]),
+.X(bcd[9]),
+.Y(dab4[1]),
+.Z(dab4[2]),
+.E(dab4[3]));
+
+dabble d5x (.A((dab3[1])),
+.B(dab3[2]),
+.C(dab3[3]),
+.D(binary[2]),
+.X(dab5[0]),
+.Y(dab5[1]),
+.Z(dab5[2]),
+.E(dab5[3]));
+
+dabble d6y (.A((dab4[1])),
+.B(dab4[2]),
+.C(dab4[3]),
+.D(dab5[0]),
+.X(bcd[8]),
+.Y(bcd[7]),
+.Z(bcd[6]),
+.E(bcd[5]));
+
+dabble d7z (.A((dab5[1])),
+.B(dab5[2]),
+.C(dab5[3]),
+.D(binary[1]),
+.X(bcd[4]),
+.Y(bcd[3]),
+.Z(bcd[2]),
+.E(bcd[1]));
+
+or o1 (bcd[0], binary[0], 1'b0);
+
+endmodule
--- a/gowin/ALU/src/addition.v
+++ b/gowin/ALU/src/addition.v
@ -0,0 +1,20 @@
+module addition (
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [2:0] Carry4;
+
+fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
+fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
+fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
+fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
+
+
+//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
+xor ov1 (overflow, Carry4[2], CarryOUT);
+
+endmodule
--- a/gowin/ALU/src/arithmeticUnit.v
+++ b/gowin/ALU/src/arithmeticUnit.v
@ -0,0 +1,33 @@
+module arithmeticUnit (
+    input [1:0] opCode,
+    input [3:0] A, B,
+    input CarryIN,
+    output [3:0] add_Y, sub_Y,
+    output CarryOUT,
+    output overflow
+);
+
+wire [3:0] addY, subY;
+wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
+
+addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
+subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
+
+and add1 (add_Y[0], opCode[0], addY[0]);
+and add2 (add_Y[1], opCode[0], addY[1]);
+and add3 (add_Y[2], opCode[0], addY[2]);
+and add4 (add_Y[3], opCode[0], addY[3]);
+
+and sub1 (sub_Y[0], opCode[1], subY[0]);
+and sub2 (sub_Y[1], opCode[1], subY[1]);
+and sub3 (sub_Y[2], opCode[1], subY[2]);
+and sub4 (sub_Y[3], opCode[1], subY[3]);
+
+// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
+and and10 (tempCSub, CarryOUTSUB, opCode[1]);
+and and11 (tempCAdd, CarryOUTADD, opCode[0]);
+or or4 (CarryOUT, tempCAdd, tempCSub);
+
+and add12 (overflow, opCode[0], tempoverflow);
+
+endmodule
--- a/gowin/ALU/src/dabble.v
+++ b/gowin/ALU/src/dabble.v
@ -0,0 +1,22 @@
+module dabble (
+    input A, B, C, D,
+    output X, Y, Z, E
+);
+
+wire xor1, nor1, xor2, nor2, nor3, or1;
+
+xor xo1 (xor1, A, D);
+nor no1 (nor1, A, B);
+xor xo2 (xor2, A, C);
+
+nor no2 (nor2, xor1, xor2);
+
+nor no3 (nor3, nor2, nor1);
+buf bu1 (X, nor3);
+or o1 (or1, xor1, nor1);
+
+nor no4 (Y, or1, C);
+and an1 (Z, or1, xor2);
+xor xo3 (E, nor3, D);
+
+endmodule
--- a/gowin/ALU/src/fulladder.v
+++ b/gowin/ALU/src/fulladder.v
@ -0,0 +1,12 @@
+module fulladder (
+    input A, B, Carry,
+    output Sum, CarryO
+);
+
+wire xor1, and1, and2;
+
+halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
+halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
+or o1 (CarryO, and1, and2);
+
+endmodule
--- a/gowin/ALU/src/fullsubtraction.v
+++ b/gowin/ALU/src/fullsubtraction.v
@ -0,0 +1,12 @@
+module fullsubtraction (
+    input A, B, BorrowIN,
+    output Difference, BorrowOut
+);
+
+wire tempD, tempB1, tempB2;
+
+halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
+halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
+or o1 (BorrowOut, tempB1, tempB2);
+
+endmodule
--- a/gowin/ALU/src/halfadder.v
+++ b/gowin/ALU/src/halfadder.v
@ -0,0 +1,9 @@
+module halfadder (
+    input A, B,
+    output Sum, Carry
+);
+
+and a1 (Carry, A, B);
+xor xo1 (Sum, A, B);
+
+endmodule
--- a/gowin/ALU/src/halfsubtraction.v
+++ b/gowin/ALU/src/halfsubtraction.v
@ -0,0 +1,12 @@
+module halfsubtraction (
+    input A, B,
+    output Difference, Borrow
+);
+
+wire notA;
+
+xor xo1 (Difference, A, B);
+not a1 (notA, A);
+and an1 (Borrow, notA, B);
+
+endmodule
--- a/gowin/ALU/src/logicUnit.v
+++ b/gowin/ALU/src/logicUnit.v
@ -0,0 +1,39 @@
+module logicUnit (
+    input [2:0] opCode,
+    input [3:0] A, B,
+    output [3:0] resultA, resultO, resultX
+);
+
+wire [3:0] and1, or1, xor1;
+
+and a01 (and1[0], A[0], B[0]);
+and a02 (and1[1], A[1], B[1]);
+and a03 (and1[2], A[2], B[2]);
+and a04 (and1[3], A[3], B[3]);
+
+or o01 (or1[0], A[0], B[0]);
+or o02 (or1[1], A[1], B[1]);
+or o03 (or1[2], A[2], B[2]);
+or o04 (or1[3], A[3], B[3]);
+
+xor xor01 (xor1[0], A[0], B[0]);
+xor xor02 (xor1[1], A[1], B[1]);
+xor xor03 (xor1[2], A[2], B[2]);
+xor xor04 (xor1[3], A[3], B[3]);
+
+and a_o1 (resultA[0], opCode[0], and1[0]);
+and a_o2 (resultA[1], opCode[0], and1[1]);
+and a_o3 (resultA[2], opCode[0], and1[2]);
+and a_o4 (resultA[3], opCode[0], and1[3]);
+
+and o_o1 (resultO[0], opCode[1], or1[0]);
+and o_o2 (resultO[1], opCode[1], or1[1]);
+and o_o3 (resultO[2], opCode[1], or1[2]);
+and o_o4 (resultO[3], opCode[1], or1[3]);
+
+and x_o1 (resultX[0], opCode[2], xor1[0]);
+and x_o2 (resultX[1], opCode[2], xor1[1]);
+and x_o3 (resultX[2], opCode[2], xor1[2]);
+and x_o4 (resultX[3], opCode[2], xor1[3]);
+
+endmodule
--- a/gowin/ALU/src/multiplier.v
+++ b/gowin/ALU/src/multiplier.v
@ -0,0 +1,76 @@
+module multiplier (
+    input [3:0] A, B,
+    output [7:0] Y
+);
+
+wire [3:0] b0, a0, a1, a2;
+wire [4:0] S0, S1, S2;
+wire carry0, carry1, carry2;
+wire overflow0, overflow1, overflow2;
+
+// Partial product generation
+and (Y[0], A[0], B[0]); // LSB of the result
+
+// Generate partial products for B[0] and B[1]
+and ab00 (b0[0], A[1], B[0]);
+and ab01 (b0[1], A[2], B[0]);
+and ab02 (b0[2], A[3], B[0]);
+not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
+
+and aa00 (a0[0], A[0], B[1]);
+and aa01 (a0[1], A[1], B[1]);
+and aa02 (a0[2], A[2], B[1]);
+and aa03 (a0[3], A[3], B[1]);
+
+// First addition
+addition add0 (
+    .A(a0),
+    .B(b0),
+    .CarryIN(1'b0),
+    .Y(S0[3:0]),
+    .CarryOUT(S0[4]),
+    .overflow(overflow0)
+);
+
+// Generate partial products for B[2]
+and aa10 (a1[0], A[0], B[2]);
+and aa11 (a1[1], A[1], B[2]);
+and aa12 (a1[2], A[2], B[2]);
+and aa13 (a1[3], A[3], B[2]);
+
+// Second addition
+addition add1 (
+    .A(a1),
+    .B(S0[4:1]),
+    .CarryIN(1'b0),
+    .Y(S1[3:0]),
+    .CarryOUT(S1[4]),
+    .overflow(overflow1)
+);
+
+// Generate partial products for B[3]
+and aa20 (a2[0], A[0], B[3]);
+and aa21 (a2[1], A[1], B[3]);
+and aa22 (a2[2], A[2], B[3]);
+and aa23 (a2[3], A[3], B[3]);
+
+// Third addition
+addition add2 (
+    .A(a2),
+    .B(S1[4:1]),
+    .CarryIN(1'b0),
+    .Y(S2[3:0]),
+    .CarryOUT(S2[4]),
+    .overflow(overflow2)
+);
+
+// Combine results into the final output Y
+or o01 (Y[1], S0[0], 1'b0);
+or o02 (Y[2], S1[0], 1'b0);
+or o03 (Y[3], S2[0], 1'b0);
+or o04 (Y[4], S2[1], 1'b0);
+or o05 (Y[5], S2[2], 1'b0);
+or o06 (Y[6], S2[3], 1'b0);
+or o07 (Y[7], S2[4], 1'b0);
+
+endmodule
--- a/gowin/ALU/src/opCode.v
+++ b/gowin/ALU/src/opCode.v
@ -0,0 +1,25 @@
+module opCode (
+    input [2:0] A,
+    output [7:0] opCode
+);
+    wire and1, and2, and3, and4, notA, notB, notC;
+
+    not n1(notA, A[2]);
+    not n2(notB, A[1]);
+    not n3(notC, A[0]);
+
+    and a01(and1, A[2], A[1]);
+    and a02(and2, notA, A[1]);
+    and a03(and3, A[2], notB);
+    and a04(and4, notA, notB);
+
+    and a1(opCode[0], and4, notC);
+    and a2(opCode[1], and4, A[0]);
+    and a3(opCode[2], and2, notC);
+    and a4(opCode[3], and2, A[0]);
+    and a5(opCode[4], and3, notC);
+    and a6(opCode[5], and3, A[0]);
+    and a7(opCode[6], and1, notC);
+    and a8(opCode[7], and1, A[0]);
+
+endmodule
--- a/gowin/ALU/src/selector.v
+++ b/gowin/ALU/src/selector.v
@ -0,0 +1,20 @@
+module selector (
+    input [3:0] A,
+    input [3:0] B,
+    input [2:0] opCodeA,
+    input [1:0] select,
+    input [11:0] ALUY,
+    output reg [11:0] Y
+);
+
+always @(*) begin
+    case (select)
+        2'b00: Y = {8'b00000000, A};          // Zero-extend A to 8 bits
+        2'b01: Y = {8'b00000000, B};          // Zero-extend B to 8 bits
+        2'b10: Y = {9'b000000000, opCodeA};   // Zero-extend opCodeA to 8 bits
+        2'b11: Y = ALUY;                  // Directly assign ALUY
+        default: Y = ALUY;         // Default case for safety
+    endcase
+end
+
+endmodule
--- a/gowin/ALU/src/subtraction.v
+++ b/gowin/ALU/src/subtraction.v
@ -0,0 +1,16 @@
+module subtraction (
+    input [3:0] A, B,
+    input BorrowIN,
+    output [3:0] Y,
+    output BorrowOUT //Overflow signal'ini yani negatif gonderecek
+);
+
+wire [3:0] tempB;
+
+// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
+fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
+fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
+fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
+fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
+
+endmodule
--- a/gowin/ALU/src/top.cst
+++ b/gowin/ALU/src/top.cst
@ -0,0 +1,65 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//Tool Version: V1.9.9.03 Education (64-bit)
+//Part Number: GW2A-LV18PG256C8/I7
+//Device: GW2A-18
+//Device Version: C
+//Created Time: Mon 01 20 17:48:00 2025
+
+IO_LOC "Y[11]" B12;
+IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[10]" B13;
+IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[9]" B14;
+IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[8]" D14;
+IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[7]" J14;
+IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[6]" M14;
+IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[5]" T12;
+IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[4]" T11;
+IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[3]" P9;
+IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[2]" P8;
+IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[1]" T7;
+IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Y[0]" P6;
+IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[1]" L14;
+IO_PORT "leds[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[0]" L16;
+IO_PORT "leds[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "Cin" E9;
+IO_PORT "Cin" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
+IO_LOC "select[1]" A14;
+IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
+IO_LOC "select[0]" A15;
+IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
+IO_LOC "opCodeA[2]" E8;
+IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
+IO_LOC "opCodeA[1]" T4;
+IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
+IO_LOC "opCodeA[0]" T5;
+IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
+IO_LOC "B[3]" N8;
+IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
+IO_LOC "B[2]" N7;
+IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
+IO_LOC "B[1]" D11;
+IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
+IO_LOC "B[0]" B11;
+IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
+IO_LOC "A[3]" L9;
+IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
+IO_LOC "A[2]" E15;
+IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
+IO_LOC "A[1]" N6;
+IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
+IO_LOC "A[0]" A11;
+IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
--- a/gowin/ALU/src/top.v
+++ b/gowin/ALU/src/top.v
@ -0,0 +1,19 @@
+module top (
+    input [3:0] A, B,
+    input [2:0] opCodeA,
+    input [1:0] select,
+    input Cin,
+    output [1:0] leds,
+    output [11:0] Y
+);
+
+
+wire wire1, wire2;
+wire [11:0] selectY;
+ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1)); //ALU module
+selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));   // selector for 7 segment
+
+assign leds[0] = ~wire1; //overflow led
+assign leds[1] = ~wire2; //CarryOut/BorrowOut led
+
+endmodule