kaltinsoy/4-bit-ALU
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k0rrluna
2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
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gowin/ALU/impl/pnr/ALU.log Normal file
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Reading netlist file: "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg"
Parsing netlist file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg" completed
Processing netlist completed
Reading constraint file: "C:\Users\koray\Documents\gowin\ALU\src\top.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.power.html" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.pin.html" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.rpt.html" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.rpt.txt" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.tr.html" completed
Thu Jan 23 05:43:13 2025