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k0rrluna
2025-01-23 06:58:05 +03:00
parent 8579de5ebc
commit 8f854d046b
193 changed files with 42478 additions and 2 deletions
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gowin/ALU/impl/gwsynthesis/ALU.prj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="C:\Users\koray\Documents\gowin\ALU\src\addition.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\ALU.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\dabble.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\fulladder.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\halfadder.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\multiplier.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\opCode.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\selector.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\subtraction.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\top.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="vcc" value="1.0"/>
<Option type="vccx" value="3.3"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>